mirror of https://github.com/openssl/openssl
riscv: Support sm3 on platforms with vlen >= 128.
This patch updates the OSSSL_HWSM3_block_data_order_zvksh and enables SM3 on platforms with VLEN >= 128. Signed-off-by: Jerry Shih <jerry.shih@sifive.com> Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com> Reviewed-by: Tomas Mraz <tomas@openssl.org> Reviewed-by: Paul Dale <pauli@openssl.org> Reviewed-by: Hugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
This commit is contained in:
Jerry Shih
Hugo Landau
parent
fbe6348363
commit
1c25bc2e3f
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@ -11,6 +11,7 @@
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# or
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#
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# Copyright (c) 2023, Christoph Müllner <christoph.muellner@vrull.eu>
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# Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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@ -36,9 +37,9 @@
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# The generated code of this file depends on the following RISC-V extensions:
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# - RV64I
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# - RISC-V vector ('V') with VLEN >= 256
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# - Vector Bit-manipulation used in Cryptography ('Zvbb')
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# - ShangMi Suite: SM3 Secure Hash ('Zvksh')
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# - RISC-V Vector ('V') with VLEN >= 128
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# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
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# - RISC-V Vector SM3 Secure Hash extension ('Zvksh')
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use strict;
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use warnings;
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@ -63,7 +64,11 @@ ___
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# ossl_hwsm3_block_data_order_zvksh(SM3_CTX *c, const void *p, size_t num);
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{
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my ($CTX, $INPUT, $NUM) = ("a0", "a1", "a2");
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my ($V0, $V1, $V2, $V3, $V4) = ("v0", "v1", "v2", "v3", "v4");
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my ($V0, $V1, $V2, $V3, $V4, $V5, $V6, $V7,
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$V8, $V9, $V10, $V11, $V12, $V13, $V14, $V15,
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$V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
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$V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
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) = map("v$_",(0..31));
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$code .= <<___;
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.text
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@ -71,142 +76,142 @@ $code .= <<___;
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.globl ossl_hwsm3_block_data_order_zvksh
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.type ossl_hwsm3_block_data_order_zvksh,\@function
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ossl_hwsm3_block_data_order_zvksh:
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@{[vsetivli__x0_8_e32_m1_tu_mu]}
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@{[vsetivli "zero", 8, "e32", "m2", "ta", "ma"]}
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# Load initial state of hash context (c->A-H).
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@{[vle32_v $V0, $CTX]}
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@{[vrev8_v $V0, $V0]}
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L_sm3_loop:
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# Copy the previous state to v1.
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# Copy the previous state to v2.
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# It will be XOR'ed with the current state at the end of the round.
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@{[vmv_v_v $V1, $V0]}
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@{[vmv_v_v $V2, $V0]}
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# Load the 64B block in 2x32B chunks.
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@{[vle32_v $V3, $INPUT]} # v3 := {w7, ..., w0}
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add $INPUT, $INPUT, 32
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@{[vle32_v $V6, $INPUT]} # v6 := {w7, ..., w0}
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addi $INPUT, $INPUT, 32
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@{[vle32_v $V4, $INPUT]} # v4 := {w15, ..., w8}
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add $INPUT, $INPUT, 32
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@{[vle32_v $V8, $INPUT]} # v8 := {w15, ..., w8}
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addi $INPUT, $INPUT, 32
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add $NUM, $NUM, -1
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addi $NUM, $NUM, -1
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# As vsm3c consumes only w0, w1, w4, w5 we need to slide the input
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# 2 elements down so we process elements w2, w3, w6, w7
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# This will be repeated for each odd round.
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@{[vslidedown_vi $V2, $V3, 2]} # v2 := {X, X, w7, ..., w2}
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@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w7, ..., w2}
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@{[vsm3c_vi $V0, $V3, 0]}
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@{[vsm3c_vi $V0, $V2, 1]}
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@{[vsm3c_vi $V0, $V6, 0]}
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@{[vsm3c_vi $V0, $V4, 1]}
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# Prepare a vector with {w11, ..., w4}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w7, ..., w4}
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@{[vslideup_vi $V2, $V4, 4]} # v2 := {w11, w10, w9, w8, w7, w6, w5, w4}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w7, ..., w4}
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@{[vslideup_vi $V4, $V8, 4]} # v4 := {w11, w10, w9, w8, w7, w6, w5, w4}
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@{[vsm3c_vi $V0, $V2, 2]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w11, w10, w9, w8, w7, w6}
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@{[vsm3c_vi $V0, $V2, 3]}
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@{[vsm3c_vi $V0, $V4, 2]}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w11, w10, w9, w8, w7, w6}
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@{[vsm3c_vi $V0, $V4, 3]}
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@{[vsm3c_vi $V0, $V4, 4]}
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@{[vslidedown_vi $V2, $V4, 2]} # v2 := {X, X, w15, w14, w13, w12, w11, w10}
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@{[vsm3c_vi $V0, $V2, 5]}
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@{[vsm3c_vi $V0, $V8, 4]}
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@{[vslidedown_vi $V4, $V8, 2]} # v4 := {X, X, w15, w14, w13, w12, w11, w10}
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@{[vsm3c_vi $V0, $V4, 5]}
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@{[vsm3me_vv $V3, $V4, $V3]} # v3 := {w23, w22, w21, w20, w19, w18, w17, w16}
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@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w23, w22, w21, w20, w19, w18, w17, w16}
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# Prepare a register with {w19, w18, w17, w16, w15, w14, w13, w12}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w15, w14, w13, w12}
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@{[vslideup_vi $V2, $V3, 4]} # v2 := {w19, w18, w17, w16, w15, w14, w13, w12}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w15, w14, w13, w12}
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@{[vslideup_vi $V4, $V6, 4]} # v4 := {w19, w18, w17, w16, w15, w14, w13, w12}
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@{[vsm3c_vi $V0, $V2, 6]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w19, w18, w17, w16, w15, w14}
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@{[vsm3c_vi $V0, $V2, 7]}
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@{[vsm3c_vi $V0, $V4, 6]}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w19, w18, w17, w16, w15, w14}
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@{[vsm3c_vi $V0, $V4, 7]}
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@{[vsm3c_vi $V0, $V3, 8]}
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@{[vslidedown_vi $V2, $V3, 2]} # v2 := {X, X, w23, w22, w21, w20, w19, w18}
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@{[vsm3c_vi $V0, $V2, 9]}
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@{[vsm3c_vi $V0, $V6, 8]}
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@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w23, w22, w21, w20, w19, w18}
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@{[vsm3c_vi $V0, $V4, 9]}
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@{[vsm3me_vv $V4, $V3, $V4]} # v4 := {w31, w30, w29, w28, w27, w26, w25, w24}
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@{[vsm3me_vv $V8, $V6, $V8]} # v8 := {w31, w30, w29, w28, w27, w26, w25, w24}
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# Prepare a register with {w27, w26, w25, w24, w23, w22, w21, w20}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w23, w22, w21, w20}
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@{[vslideup_vi $V2, $V4, 4]} # v2 := {w27, w26, w25, w24, w23, w22, w21, w20}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w23, w22, w21, w20}
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@{[vslideup_vi $V4, $V8, 4]} # v4 := {w27, w26, w25, w24, w23, w22, w21, w20}
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@{[vsm3c_vi $V0, $V2, 10]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w27, w26, w25, w24, w23, w22}
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@{[vsm3c_vi $V0, $V2, 11]}
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@{[vsm3c_vi $V0, $V4, 10]}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w27, w26, w25, w24, w23, w22}
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@{[vsm3c_vi $V0, $V4, 11]}
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@{[vsm3c_vi $V0, $V4, 12]}
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@{[vslidedown_vi $V2, $V4, 2]} # v2 := {x, X, w31, w30, w29, w28, w27, w26}
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@{[vsm3c_vi $V0, $V2, 13]}
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@{[vsm3c_vi $V0, $V8, 12]}
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@{[vslidedown_vi $V4, $V8, 2]} # v4 := {x, X, w31, w30, w29, w28, w27, w26}
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@{[vsm3c_vi $V0, $V4, 13]}
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@{[vsm3me_vv $V3, $V4, $V3]} # v3 := {w32, w33, w34, w35, w36, w37, w38, w39}
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@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w32, w33, w34, w35, w36, w37, w38, w39}
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# Prepare a register with {w35, w34, w33, w32, w31, w30, w29, w28}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w31, w30, w29, w28}
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@{[vslideup_vi $V2, $V3, 4]} # v2 := {w35, w34, w33, w32, w31, w30, w29, w28}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w31, w30, w29, w28}
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@{[vslideup_vi $V4, $V6, 4]} # v4 := {w35, w34, w33, w32, w31, w30, w29, w28}
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@{[vsm3c_vi $V0, $V2, 14]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w35, w34, w33, w32, w31, w30}
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@{[vsm3c_vi $V0, $V2, 15]}
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@{[vsm3c_vi $V0, $V4, 14]}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w35, w34, w33, w32, w31, w30}
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@{[vsm3c_vi $V0, $V4, 15]}
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@{[vsm3c_vi $V0, $V3, 16]}
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@{[vslidedown_vi $V2, $V3, 2]} # v2 := {X, X, w39, w38, w37, w36, w35, w34}
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@{[vsm3c_vi $V0, $V2, 17]}
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@{[vsm3c_vi $V0, $V6, 16]}
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@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w39, w38, w37, w36, w35, w34}
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@{[vsm3c_vi $V0, $V4, 17]}
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@{[vsm3me_vv $V4, $V3, $V4]} # v4 := {w47, w46, w45, w44, w43, w42, w41, w40}
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@{[vsm3me_vv $V8, $V6, $V8]} # v8 := {w47, w46, w45, w44, w43, w42, w41, w40}
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# Prepare a register with {w43, w42, w41, w40, w39, w38, w37, w36}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w39, w38, w37, w36}
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@{[vslideup_vi $V2, $V4, 4]} # v2 := {w43, w42, w41, w40, w39, w38, w37, w36}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w39, w38, w37, w36}
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@{[vslideup_vi $V4, $V8, 4]} # v4 := {w43, w42, w41, w40, w39, w38, w37, w36}
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@{[vsm3c_vi $V0, $V2, 18]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w43, w42, w41, w40, w39, w38}
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@{[vsm3c_vi $V0, $V2, 19]}
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@{[vsm3c_vi $V0, $V4, 18]}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w43, w42, w41, w40, w39, w38}
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@{[vsm3c_vi $V0, $V4, 19]}
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@{[vsm3c_vi $V0, $V4, 20]}
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@{[vslidedown_vi $V2, $V4, 2]} # v2 := {X, X, w47, w46, w45, w44, w43, w42}
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@{[vsm3c_vi $V0, $V2, 21]}
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@{[vsm3c_vi $V0, $V8, 20]}
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@{[vslidedown_vi $V4, $V8, 2]} # v4 := {X, X, w47, w46, w45, w44, w43, w42}
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@{[vsm3c_vi $V0, $V4, 21]}
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@{[vsm3me_vv $V3, $V4, $V3]} # v3 := {w55, w54, w53, w52, w51, w50, w49, w48}
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@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w55, w54, w53, w52, w51, w50, w49, w48}
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# Prepare a register with {w51, w50, w49, w48, w47, w46, w45, w44}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w47, w46, w45, w44}
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@{[vslideup_vi $V2, $V3, 4]} # v2 := {w51, w50, w49, w48, w47, w46, w45, w44}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w47, w46, w45, w44}
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@{[vslideup_vi $V4, $V6, 4]} # v4 := {w51, w50, w49, w48, w47, w46, w45, w44}
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@{[vsm3c_vi $V0, $V2, 22]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w51, w50, w49, w48, w47, w46}
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@{[vsm3c_vi $V0, $V2, 23]}
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@{[vsm3c_vi $V0, $V4, 22]}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w51, w50, w49, w48, w47, w46}
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@{[vsm3c_vi $V0, $V4, 23]}
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@{[vsm3c_vi $V0, $V3, 24]}
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@{[vslidedown_vi $V2, $V3, 2]} # v2 := {X, X, w55, w54, w53, w52, w51, w50}
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@{[vsm3c_vi $V0, $V2, 25]}
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@{[vsm3c_vi $V0, $V6, 24]}
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@{[vslidedown_vi $V4, $V6, 2]} # v4 := {X, X, w55, w54, w53, w52, w51, w50}
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@{[vsm3c_vi $V0, $V4, 25]}
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@{[vsm3me_vv $V4, $V3, $V4]} # v4 := {w63, w62, w61, w60, w59, w58, w57, w56}
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@{[vsm3me_vv $V8, $V6, $V8]} # v8 := {w63, w62, w61, w60, w59, w58, w57, w56}
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# Prepare a register with {w59, w58, w57, w56, w55, w54, w53, w52}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w55, w54, w53, w52}
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@{[vslideup_vi $V2, $V4, 4]} # v2 := {w59, w58, w57, w56, w55, w54, w53, w52}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w55, w54, w53, w52}
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@{[vslideup_vi $V4, $V8, 4]} # v4 := {w59, w58, w57, w56, w55, w54, w53, w52}
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@{[vsm3c_vi $V0, $V2, 26]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w59, w58, w57, w56, w55, w54}
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@{[vsm3c_vi $V0, $V2, 27]}
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@{[vsm3c_vi $V0, $V4, 26]}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w59, w58, w57, w56, w55, w54}
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@{[vsm3c_vi $V0, $V4, 27]}
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@{[vsm3c_vi $V0, $V4, 28]}
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@{[vslidedown_vi $V2, $V4, 2]} # v2 := {X, X, w63, w62, w61, w60, w59, w58}
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@{[vsm3c_vi $V0, $V2, 29]}
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@{[vsm3c_vi $V0, $V8, 28]}
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@{[vslidedown_vi $V4, $V8, 2]} # v4 := {X, X, w63, w62, w61, w60, w59, w58}
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@{[vsm3c_vi $V0, $V4, 29]}
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@{[vsm3me_vv $V3, $V4, $V3]} # v3 := {w71, w70, w69, w68, w67, w66, w65, w64}
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@{[vsm3me_vv $V6, $V8, $V6]} # v6 := {w71, w70, w69, w68, w67, w66, w65, w64}
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# Prepare a register with {w67, w66, w65, w64, w63, w62, w61, w60}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, X, X, w63, w62, w61, w60}
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@{[vslideup_vi $V2, $V3, 4]} # v2 := {w67, w66, w65, w64, w63, w62, w61, w60}
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@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, X, X, w63, w62, w61, w60}
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@{[vslideup_vi $V4, $V6, 4]} # v4 := {w67, w66, w65, w64, w63, w62, w61, w60}
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@{[vsm3c_vi $V0, $V2, 30]}
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@{[vslidedown_vi $V2, $V2, 2]} # v2 := {X, X, w67, w66, w65, w64, w63, w62}
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@{[vsm3c_vi $V0, $V2, 31]}
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@{[vsm3c_vi $V0, $V4, 30]}
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||||
@{[vslidedown_vi $V4, $V4, 2]} # v4 := {X, X, w67, w66, w65, w64, w63, w62}
|
||||
@{[vsm3c_vi $V0, $V4, 31]}
|
||||
|
||||
# XOR in the previous state.
|
||||
@{[vxor_vv $V0, $V0, $V1]}
|
||||
@{[vxor_vv $V0, $V0, $V2]}
|
||||
|
||||
bnez $NUM, L_sm3_loop # Check if there are any more block to process
|
||||
L_sm3_end:
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
|
|||
|
||||
void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num)
|
||||
{
|
||||
if (RISCV_HAS_ZVBB_AND_ZVKSH() && riscv_vlen() >= 256) {
|
||||
if (RISCV_HAS_ZVKB_AND_ZVKSH() && riscv_vlen() >= 128) {
|
||||
ossl_hwsm3_block_data_order_zvksh(c, p, num);
|
||||
} else {
|
||||
ossl_sm3_block_data_order(c, p, num);
|
||||
|
|
|
|||
Loading…
Reference in New Issue