mirror of https://github.com/openssl/openssl
RC4 tune-up for Intel P4 core, both 32- and 64-bit ones. As it's
apparently impossible to compose blended code with would perform satisfactory on all x86 and x86_64 cores, an extra RC4_CHAR code-path is introduced and P4 core is detected at run-time. This way we keep original performance on non-P4 implementations and turbo-charge P4 performance by factor of 2.8x (on 32-bit core).
This commit is contained in:
Andy Polyakov
parent
00dd8f6d6e
commit
376729e130
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@ -318,7 +318,7 @@ my %table=(
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"linux-s390x", "gcc:-DB_ENDIAN -DTERMIO -DNO_ASM -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG:${no_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-ia64", "gcc:-DL_ENDIAN -DTERMIO -O3 -Wall::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHUNK RC4_CHAR::asm/ia64.o::asm/aes-ia64.o:::asm/sha256-ia64.o asm/sha512-ia64.o:::::dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-ia64-ecc","ecc:-DL_ENDIAN -DTERMIO -O2 -Wall -no_cpprt::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHUNK RC4_CHAR::asm/ia64.o::asm/aes-ia64.o:::asm/sha256-ia64.o asm/sha512-ia64.o:::::dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-x86_64", "gcc:-m64 -DL_ENDIAN -DTERMIO -O3 -Wall -DMD32_REG_T=int::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHUNK BF_PTR2 DES_INT DES_UNROLL::asm/x86_64-gcc.o:::::::asm/rc4-amd64.o:::dlfcn:linux-shared:-fPIC:-m64:.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-x86_64", "gcc:-m64 -DL_ENDIAN -DTERMIO -O3 -Wall -DMD32_REG_T=int::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHUNK BF_PTR2 DES_INT DES_UNROLL:amd64cpuid.o:asm/x86_64-gcc.o:::::::asm/rc4-amd64.o:::dlfcn:linux-shared:-fPIC:-m64:.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-elf-arm","gcc:-DL_ENDIAN -DTERMIO -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:BN_LLONG:${no_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)",
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"linux-parisc", "gcc:-DB_ENDIAN -DTERMIO -O3 -fomit-frame-pointer -Wall -DBN_DIV2W::-D_REENTRANT:::BN_LLONG RC4_CHAR RC4_CHUNK DES_UNROLL BF_PTR::",
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#### SPARC Linux setups
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4
TABLE
4
TABLE
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@ -2086,7 +2086,7 @@ $unistd =
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$thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -rdynamic -ldl
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$bn_ops = DES_PTR DES_RISC1 DES_UNROLL RC4_INDEX MD2_INT
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$bn_ops = BN_LLONG DES_PTR DES_RISC1 DES_UNROLL RC4_INDEX MD2_INT
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$cpuid_obj = x86cpuid-elf.o
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$bn_obj = asm/bn86-elf.o asm/co86-elf.o
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$des_obj = asm/dx86-elf.o asm/yx86-elf.o
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@ -3572,7 +3572,7 @@ $thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -ldl
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$bn_ops = SIXTY_FOUR_BIT_LONG RC4_CHUNK BF_PTR2 DES_INT DES_UNROLL
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$cpuid_obj =
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$cpuid_obj = amd64cpuid.o
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$bn_obj = asm/x86_64-gcc.o
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$des_obj =
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$aes_obj =
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@ -5,16 +5,63 @@ $win64a=1 if ($output =~ /win64a\.[s|asm]/);
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open STDOUT,">$output" || die "can't open $output: $!";
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print<<___ if(defined($win64a));
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TEXT SEGMENT
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_TEXT SEGMENT
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PUBLIC OPENSSL_rdtsc
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ALIGN 16
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OPENSSL_rdtsc PROC NEAR
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OPENSSL_rdtsc PROC
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rdtsc
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shl rdx,32
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or rax,rdx
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ret
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OPENSSL_rdtsc ENDP
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TEXT ENDS
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PUBLIC OPENSSL_atomic_add
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ALIGN 16
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OPENSSL_atomic_add PROC
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mov eax,DWORD PTR[rcx]
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\$Lspin: lea r8,DWORD PTR[rdx+rax]
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lock cmpxchg DWORD PTR[rcx],r8d
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jne \$Lspin
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mov eax,r8d
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cdqe
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ret
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OPENSSL_atomic_add ENDP
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PUBLIC OPENSSL_wipe_cpu
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ALIGN 16
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OPENSSL_wipe_cpu PROC
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pxor xmm0,xmm0
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pxor xmm1,xmm1
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pxor xmm2,xmm2
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pxor xmm3,xmm3
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pxor xmm4,xmm4
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pxor xmm5,xmm5
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xor rcx,rcx
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xor rdx,rdx
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xor r8,r8
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xor r9,r9
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xor r10,r10
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xor r11,r11
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lea rax,QWORD PTR[rsp+8]
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ret
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OPENSSL_wipe_cpu ENDP
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OPENSSL_ia32_cpuid PROC
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mov r8,rbx
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mov eax,1
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cpuid
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shl rcx,32
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mov eax,edx
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mov rbx,r8
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or rax,rcx
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ret
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OPENSSL_ia32_cpuid ENDP
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_TEXT ENDS
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CRT\$XIU SEGMENT
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EXTRN OPENSSL_cpuid_setup:PROC
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DQ OPENSSL_cpuid_setup
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CRT\$XIU ENDS
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END
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___
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print<<___ if(!defined($win64a));
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@ -27,4 +74,66 @@ OPENSSL_rdtsc:
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or %rdx,%rax
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ret
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.size OPENSSL_rdtsc,.-OPENSSL_rdtsc
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.globl OPENSSL_atomic_add
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.type OPENSSL_atomic_add,\@function
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.align 16
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OPENSSL_atomic_add:
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movl (%rdi),%eax
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.Lspin: lea (%rsi,%rax),%r8
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lock; cmpxchg %r8d,(%rdi)
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jne .Lspin
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mov %r8d,%eax
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cdqe
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ret
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.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
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.globl OPENSSL_wipe_cpu
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.type OPENSSL_wipe_cpu,\@function
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.align 16
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OPENSSL_wipe_cpu:
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pxor %xmm0,%xmm0
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pxor %xmm1,%xmm1
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pxor %xmm2,%xmm2
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pxor %xmm3,%xmm3
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pxor %xmm4,%xmm4
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pxor %xmm5,%xmm5
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pxor %xmm6,%xmm6
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pxor %xmm7,%xmm7
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pxor %xmm8,%xmm8
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pxor %xmm9,%xmm9
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pxor %xmm10,%xmm10
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pxor %xmm11,%xmm11
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pxor %xmm12,%xmm12
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pxor %xmm13,%xmm13
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pxor %xmm14,%xmm14
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pxor %xmm15,%xmm15
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xor %rcx,%rcx
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xor %rdx,%rdx
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xor %rsi,%rsi
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xor %rdi,%rdi
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xor %r8,%r8
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xor %r9,%r9
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xor %r10,%r10
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xor %r11,%r11
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lea 8(%rsp),%rax
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ret
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.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
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.globl OPENSSL_ia32_cpuid
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.align 16
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OPENSSL_ia32_cpuid:
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mov %rbx,%r8
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mov \$1,%eax
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cpuid
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shl \$32,%rcx
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mov %edx,%eax
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mov %r8,%rbx
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or %rcx,%rax
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ret
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.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid
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.section .init
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call OPENSSL_cpuid_setup
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.align 16
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___
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@ -161,7 +161,7 @@ sub main'shl { &out2("sall",@_); }
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sub main'shr { &out2("shrl",@_); }
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sub main'xor { &out2("xorl",@_); }
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sub main'xorb { &out2("xorb",@_); }
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sub main'add { &out2("addl",@_); }
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sub main'add { &out2($_[0]=~/%[a-d][lh]/?"addb":"addl",@_); }
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sub main'adc { &out2("adcl",@_); }
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sub main'sub { &out2("subl",@_); }
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sub main'sbb { &out2("sbbl",@_); }
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@ -189,7 +189,7 @@ sub main'jc { &out1("jc",@_); }
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sub main'jnc { &out1("jnc",@_); }
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sub main'jno { &out1("jno",@_); }
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sub main'dec { &out1("decl",@_); }
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sub main'inc { &out1("incl",@_); }
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sub main'inc { &out1($_[0]=~/%[a-d][hl]/?"incb":"incl",@_); }
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sub main'push { &out1("pushl",@_); $stack+=4; }
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sub main'pop { &out1("popl",@_); $stack-=4; }
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sub main'pushf { &out0("pushfl"); $stack+=4; }
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@ -205,9 +205,10 @@ sub main'nop { &out0("nop"); }
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sub main'test { &out2("testl",@_); }
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sub main'bt { &out2("btl",@_); }
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sub main'leave { &out0("leave"); }
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sub main'cpuid { &out0(".byte 0x0f; .byte 0xa2"); }
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sub main'rdtsc { &out0(".byte 0x0f; .byte 0x31"); }
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sub main'cpuid { &out0(".byte\t0x0f,0xa2"); }
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sub main'rdtsc { &out0(".byte\t0x0f,0x31"); }
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sub main'halt { &out0("hlt"); }
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sub main'movz { &out2("movzb",@_); }
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# SSE2
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sub main'emms { &out0("emms"); }
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@ -558,7 +559,7 @@ sub main'file_end
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pushl %ebx
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movl %edx,%edi
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movl \$1,%eax
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.byte 0x0f; .byte 0xa2
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.byte 0x0f,0xa2
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orl \$1<<10,%edx
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movl %edx,0(%edi)
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popl %ebx
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@ -7,10 +7,10 @@ require "x86asm.pl";
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&asm_init($ARGV[0],"rc4-586.pl");
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$tx="eax";
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$ty="ebx";
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$x="ecx";
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$y="edx";
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$x="eax";
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$y="ebx";
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$tx="ecx";
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$ty="edx";
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$in="esi";
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$out="edi";
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$d="ebp";
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@ -31,7 +31,7 @@ sub RC4_loop
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{
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&mov($ty, &swtmp(2));
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&cmp($ty, $in);
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&jle(&label("finished"));
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&jbe(&label("finished"));
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&inc($in);
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}
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else
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@ -39,7 +39,7 @@ sub RC4_loop
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&add($ty, 8);
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&inc($in);
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&cmp($ty, $in);
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&jl(&label("finished"));
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&jb(&label("finished"));
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&mov(&swtmp(2), $ty);
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}
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}
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@ -88,35 +88,44 @@ sub RC4
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&function_begin_B($name,"");
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&mov($ty,&wparam(1)); # len
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&cmp($ty,0);
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&jne(&label("proceed"));
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&ret();
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&set_label("proceed");
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&comment("");
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&push("ebp");
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&push("ebx");
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&mov( $d, &wparam(0)); # key
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&mov( $ty, &wparam(1)); # num
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&push("esi");
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&push("edi");
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&mov( $d, &wparam(0)); # key
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&mov( $in, &wparam(2));
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&mov( $x, &DWP(0,$d,"",1));
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&mov( $y, &DWP(4,$d,"",1));
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&mov( $in, &wparam(2));
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&mov( $out, &wparam(3));
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&inc( $x);
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&stack_push(3); # 3 temp variables
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&add( $d, 8);
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&and( $x, 0xff);
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# detect compressed schedule, see commentary section in rc4_skey.c...
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&cmp(&DWP(256,$d),-1);
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&je(&label("RC4_CHAR"));
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&lea( $ty, &DWP(-8,$ty,$in));
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# check for 0 length input
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&mov( $out, &wparam(3));
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&mov( &swtmp(2), $ty); # this is now address to exit at
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&mov( $tx, &DWP(0,$d,$x,4));
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&cmp( $ty, $in);
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&jl( &label("end")); # less than 8 bytes
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&jb( &label("end")); # less than 8 bytes
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&set_label("start");
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@ -148,7 +157,7 @@ sub RC4
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&mov( &DWP(-4,$out,"",0), $tx);
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&mov( $tx, &DWP(0,$d,$x,4));
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&cmp($in, $ty);
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&jle(&label("start"));
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&jbe(&label("start"));
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&set_label("end");
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@ -162,6 +171,32 @@ sub RC4
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&RC4_loop(5,0,1);
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&RC4_loop(6,1,1);
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&jmp(&label("finished"));
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&align(16);
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# this is essentially Intel P4 specific codepath, see rc4_skey.c...
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&set_label("RC4_CHAR");
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&lea ($ty,&DWP(0,$in,$ty));
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&mov (&swtmp(2),$ty);
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# strangely enough unrolled loop performs over 20% slower...
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&set_label("RC4_CHAR_loop");
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&movz ($tx,&BP(0,$d,$x));
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&add (&LB($y),&LB($tx));
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&movz ($ty,&BP(0,$d,$y));
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&movb (&BP(0,$d,$y),&LB($tx));
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&movb (&BP(0,$d,$x),&LB($ty));
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&add (&LB($ty),&LB($tx));
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&movz ($ty,&BP(0,$d,$ty));
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&xorb (&LB($ty),&BP(0,$in));
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&movb (&BP(0,$out),&LB($ty));
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&inc (&LB($x));
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&inc ($in);
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&inc ($out);
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&cmp ($in,&swtmp(2));
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&jb (&label("RC4_CHAR_loop"));
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&set_label("finished");
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&dec( $x);
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&stack_pop(3);
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@ -25,6 +25,13 @@
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# Latter means that if you want to *estimate* what to expect from
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# *your* CPU, then multiply 54 by 3.3 and clock frequency in GHz.
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# Intel P4 EM64T core was found to run the AMD64 code really slow...
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# The only way to achieve comparable performance on P4 is to keep
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# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
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# compose blended code, which would perform even within 30% marginal
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# on either AMD and Intel platforms, I implement both cases. See
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# rc4_skey.c for further details...
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$output=shift;
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$win64a=1 if ($output =~ /win64a.[s|asm]/);
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@ -90,6 +97,8 @@ $code.=<<___;
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add \$8,$dat
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movl `&PTR("DWORD:-8[$dat]")`,$XX#d
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movl `&PTR("DWORD:-4[$dat]")`,$YY#d
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cmpl \$-1,`&PTR("DWORD:256[$dat]")`
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je .LRC4_CHAR
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test \$-8,$len
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jz .Lloop1
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.align 16
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@ -167,6 +176,24 @@ $code.=<<___;
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dec $len
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jnz .Lloop1
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jmp .Lexit
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.align 16
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.LRC4_CHAR:
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inc $XX#b
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movzb `&PTR("BYTE:[$dat+$XX]")`,$TX#d
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add $TX#b,$YY#b
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movzb `&PTR("BYTE:[$dat+$YY]")`,$TY#d
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movb $TX#b,`&PTR("BYTE:[$dat+$YY]")`
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movb $TY#b,`&PTR("BYTE:[$dat+$XX]")`
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add $TX#b,$TY#b
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movzb `&PTR("BYTE:[$dat+$TY]")`,$TY#d
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xorb `&PTR("BYTE:[$inp]")`,$TY#b
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movb $TY#b,`&PTR("BYTE:[$out]")`
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inc $inp
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inc $out
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dec $len
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jnz .LRC4_CHAR
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jmp .Lexit
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___
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$code.=<<___ if (defined($win64a));
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RC4 ENDP
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@ -189,6 +216,8 @@ if (defined($win64a)) {
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$code =~ s/mov[bwlq]/mov/gm;
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$code =~ s/movzb/movzx/gm;
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$code =~ s/repret/DB\t0F3h,0C3h/gm;
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$code =~ s/cmpl/cmp/gm;
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$code =~ s/xorb/xor/gm;
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} else {
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$code =~ s/([QD]*WORD|BYTE)://gm;
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$code =~ s/repret/.byte\t0xF3,0xC3/gm;
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@ -1,4 +1,5 @@
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#ifndef HEADER_RC4_LOCL_H
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#define HEADER_RC4_LOCL_H
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#include <openssl/opensslconf.h>
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#include <cryptlib.h>
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#endif
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|
|
@ -93,25 +93,58 @@ void RC4_set_key(RC4_KEY *key, int len, const unsigned char *data)
|
|||
unsigned int i;
|
||||
|
||||
d= &(key->data[0]);
|
||||
for (i=0; i<256; i++)
|
||||
d[i]=i;
|
||||
key->x = 0;
|
||||
key->y = 0;
|
||||
id1=id2=0;
|
||||
|
||||
#define SK_LOOP(n) { \
|
||||
#define SK_LOOP(d,n) { \
|
||||
tmp=d[(n)]; \
|
||||
id2 = (data[id1] + tmp + id2) & 0xff; \
|
||||
if (++id1 == len) id1=0; \
|
||||
d[(n)]=d[id2]; \
|
||||
d[id2]=tmp; }
|
||||
|
||||
#if defined(OPENSSL_CPUID_OBJ) && !defined(OPENSSL_NO_ASM)
|
||||
# if defined(__i386) || defined(__i386__) || defined(_M_IX86) || \
|
||||
defined(__INTEL__) || \
|
||||
defined(__x86_64) || defined(__x86_64__) || defined(_M_AMD64)
|
||||
if (sizeof(RC4_INT) > 1) {
|
||||
/*
|
||||
* Unlike all other x86 [and x86_64] implementations,
|
||||
* Intel P4 core [including EM64T] was found to perform
|
||||
* poorly with wider RC4_INT. Performance improvement
|
||||
* for IA-32 hand-coded assembler turned out to be 2.8x
|
||||
* if re-coded for RC4_CHAR! It's however inappropriate
|
||||
* to just switch to RC4_CHAR for x86[_64], as non-P4
|
||||
* implementations suffer from significant performance
|
||||
* losses then, e.g. PIII exhibits >2x deterioration,
|
||||
* and so does Opteron. In order to assure optimal
|
||||
* all-round performance, let us [try to] detect P4 at
|
||||
* run-time by checking upon HTT bit in CPU capability
|
||||
* vector and set up compressed key schedule, which is
|
||||
* recognized by correspondingly updated assembler
|
||||
* module...
|
||||
* <appro@fy.chalmers.se>
|
||||
*/
|
||||
if (OPENSSL_ia32cap_P & (1<<28)) {
|
||||
unsigned char *cp=(unsigned char *)d;
|
||||
|
||||
for (i=0;i<256;i++) cp[i]=i;
|
||||
for (i=0;i<256;i++) SK_LOOP(cp,i);
|
||||
/* mark schedule as compressed! */
|
||||
d[256/sizeof(RC4_INT)]=-1;
|
||||
return;
|
||||
}
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
for (i=0; i < 256; i++) d[i]=i;
|
||||
for (i=0; i < 256; i+=4)
|
||||
{
|
||||
SK_LOOP(i+0);
|
||||
SK_LOOP(i+1);
|
||||
SK_LOOP(i+2);
|
||||
SK_LOOP(i+3);
|
||||
SK_LOOP(d,i+0);
|
||||
SK_LOOP(d,i+1);
|
||||
SK_LOOP(d,i+2);
|
||||
SK_LOOP(d,i+3);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,11 +14,12 @@ OPENSSL_ia32cap
|
|||
Value returned by OPENSSL_ia32cap_loc() is address of a variable
|
||||
containing IA-32 processor capabilities bit vector as it appears in EDX
|
||||
register after executing CPUID instruction with EAX=1 input value (see
|
||||
Intel Application Note #241618). Naturally it's meaningful on IA-32
|
||||
Intel Application Note #241618). Naturally it's meaningful on IA-32[E]
|
||||
platforms only. The variable is normally set up automatically upon
|
||||
toolkit initialization, but can be manipulated afterwards to modify
|
||||
crypto library behaviour. For the moment of this writing only two bits
|
||||
are significant, namely bit #26 denoting SSE2 support, and bit #4
|
||||
crypto library behaviour. For the moment of this writing three bits are
|
||||
significant, namely bit #28 denoting Hyperthreading, which is used to
|
||||
distinguish Intel P4 core, bit #26 denoting SSE2 support, and bit #4
|
||||
denoting presence of Time-Stamp Counter. Clearing bit #26 at run-time
|
||||
for example disables high-performance SSE2 code present in the crypto
|
||||
library. You might have to do this if target OpenSSL application is
|
||||
|
|
|
|||
Loading…
Reference in New Issue