mirror of https://github.com/openssl/openssl
Engage GHASH for ARMv8.
This commit is contained in:
Andy Polyakov
parent
2d5a799d27
commit
82741e9c89
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@ -136,8 +136,8 @@ my $alpha_asm="alphacpuid.o:bn_asm.o alpha-mont.o:::::sha1-alpha.o:::::::ghash-a
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my $mips64_asm=":bn-mips.o mips-mont.o::aes_cbc.o aes-mips.o:::sha1-mips.o sha256-mips.o sha512-mips.o::::::::";
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my $mips32_asm=$mips64_asm; $mips32_asm =~ s/\s*sha512\-mips\.o//;
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my $s390x_asm="s390xcap.o s390xcpuid.o:bn-s390x.o s390x-mont.o s390x-gf2m.o::aes-s390x.o aes-ctr.o aes-xts.o:::sha1-s390x.o sha256-s390x.o sha512-s390x.o::rc4-s390x.o:::::ghash-s390x.o:";
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my $armv4_asm="armcap.o armv4cpuid.o:bn_asm.o armv4-mont.o armv4-gf2m.o::aes_cbc.o aes-armv4.o bsaes-armv7.o aesv8-armx.o:::sha1-armv4-large.o sha256-armv4.o sha512-armv4.o:::::::ghash-armv4.o::void";
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my $aarch64_asm="armcap.o arm64cpuid.o mem_clr.o:::aes_core.o aes_cbc.o aesv8-armx.o:::sha1-armv8.o sha256-armv8.o sha512-armv8.o::::::::";
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my $armv4_asm="armcap.o armv4cpuid.o:bn_asm.o armv4-mont.o armv4-gf2m.o::aes_cbc.o aes-armv4.o bsaes-armv7.o aesv8-armx.o:::sha1-armv4-large.o sha256-armv4.o sha512-armv4.o:::::::ghash-armv4.o ghashv8-armx.o::void";
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my $aarch64_asm="armcap.o arm64cpuid.o mem_clr.o:::aes_core.o aes_cbc.o aesv8-armx.o:::sha1-armv8.o sha256-armv8.o sha512-armv8.o:::::::ghashv8-armx.o:";
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my $parisc11_asm="pariscid.o:bn_asm.o parisc-mont.o::aes_core.o aes_cbc.o aes-parisc.o:::sha1-parisc.o sha256-parisc.o sha512-parisc.o::rc4-parisc.o:::::ghash-parisc.o::32";
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my $parisc20_asm="pariscid.o:pa-risc2W.o parisc-mont.o::aes_core.o aes_cbc.o aes-parisc.o:::sha1-parisc.o sha256-parisc.o sha512-parisc.o::rc4-parisc.o:::::ghash-parisc.o::64";
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my $ppc64_asm="ppccpuid.o ppccap.o:bn-ppc.o ppc-mont.o ppc64-mont.o::aes_core.o aes_cbc.o aes-ppc.o vpaes-ppc.o aesp8-ppc.o:::sha1-ppc.o sha256-ppc.o sha512-ppc.o::::::::";
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@ -1617,7 +1617,7 @@ else {
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$wp_obj="wp_block.o";
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}
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$cmll_obj=$cmll_enc unless ($cmll_obj =~ /.o$/);
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if ($modes_obj =~ /ghash/)
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if ($modes_obj =~ /ghash\-/)
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{
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$cflags.=" -DGHASH_ASM";
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}
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6
TABLE
6
TABLE
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@ -1110,7 +1110,7 @@ $rmd160_obj =
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$rc5_obj =
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$wp_obj =
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$cmll_obj =
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$modes_obj = ghash-armv4.o
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$modes_obj = ghash-armv4.o ghashv8-armx.o
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$engines_obj =
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$perlasm_scheme = void
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$dso_scheme = dlfcn
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@ -4014,7 +4014,7 @@ $rmd160_obj =
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$rc5_obj =
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$wp_obj =
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$cmll_obj =
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$modes_obj =
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$modes_obj = ghashv8-armx.o
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$engines_obj =
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$perlasm_scheme = linux64
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$dso_scheme = dlfcn
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@ -4212,7 +4212,7 @@ $rmd160_obj =
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$rc5_obj =
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$wp_obj =
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$cmll_obj =
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$modes_obj = ghash-armv4.o
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$modes_obj = ghash-armv4.o ghashv8-armx.o
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$engines_obj =
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$perlasm_scheme = void
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$dso_scheme = dlfcn
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@ -58,14 +58,16 @@ ghash-alpha.s: asm/ghash-alpha.pl
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(preproc=/tmp/$$$$.$@; trap "rm $$preproc" INT; \
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$(PERL) asm/ghash-alpha.pl > $$preproc && \
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$(CC) -E $$preproc > $@ && rm $$preproc)
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ghash-parisc.s: asm/ghash-parisc.pl
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$(PERL) asm/ghash-parisc.pl $(PERLASM_SCHEME) $@
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ghashv8-armx.S: asm/ghashv8-armx.pl
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$(PERL) asm/ghashv8-armx.pl $(PERLASM_SCHEME) $@
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# GNU make "catch all"
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ghash-%.S: asm/ghash-%.pl; $(PERL) $< $(PERLASM_SCHEME) $@
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ghash-armv4.o: ghash-armv4.S
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ghashv8-armx.o: ghashv8-armx.S
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files:
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$(PERL) $(TOP)/util/files.pl Makefile >> $(TOP)/MINFO
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@ -645,7 +645,7 @@ static void gcm_gmult_1bit(u64 Xi[2],const u64 H[2])
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#endif
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#if TABLE_BITS==4 && defined(GHASH_ASM)
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#if TABLE_BITS==4 && (defined(GHASH_ASM) || defined(OPENSSL_CPUID_OBJ))
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# if !defined(I386_ONLY) && \
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(defined(__i386) || defined(__i386__) || \
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defined(__x86_64) || defined(__x86_64__) || \
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@ -676,14 +676,21 @@ void gcm_ghash_4bit_mmx(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len
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void gcm_gmult_4bit_x86(u64 Xi[2],const u128 Htable[16]);
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void gcm_ghash_4bit_x86(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
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# endif
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# elif defined(__arm__) || defined(__arm)
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# elif defined(__arm__) || defined(__arm) || defined(__aarch64__)
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# include "arm_arch.h"
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# if __ARM_ARCH__>=7
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# define GHASH_ASM_ARM
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# define GCM_FUNCREF_4BIT
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# define PMULL_CAPABLE (OPENSSL_armcap_P & ARMV8_PMULL)
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# if defined(__arm__) || defined(__arm)
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# define NEON_CAPABLE (OPENSSL_armcap_P & ARMV7_NEON)
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# endif
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void gcm_init_neon(u128 Htable[16],const u64 Xi[2]);
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void gcm_gmult_neon(u64 Xi[2],const u128 Htable[16]);
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void gcm_ghash_neon(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
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void gcm_init_v8(u128 Htable[16],const u64 Xi[2]);
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void gcm_gmult_v8(u64 Xi[2],const u128 Htable[16]);
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void gcm_ghash_v8(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
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# endif
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# elif defined(__sparc__) || defined(__sparc)
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# include "sparc_arch.h"
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@ -767,11 +774,21 @@ void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx,void *key,block128_f block)
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ctx->ghash = gcm_ghash_4bit;
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# endif
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# elif defined(GHASH_ASM_ARM)
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if (OPENSSL_armcap_P & ARMV7_NEON) {
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# ifdef PMULL_CAPABLE
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if (PMULL_CAPABLE) {
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gcm_init_v8(ctx->Htable,ctx->H.u);
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ctx->gmult = gcm_gmult_v8;
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ctx->ghash = gcm_ghash_v8;
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} else
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# endif
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# ifdef NEON_CAPABLE
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if (NEON_CAPABLE) {
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gcm_init_neon(ctx->Htable,ctx->H.u);
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ctx->gmult = gcm_gmult_neon;
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ctx->ghash = gcm_ghash_neon;
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} else {
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} else
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# endif
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{
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gcm_init_4bit(ctx->Htable,ctx->H.u);
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ctx->gmult = gcm_gmult_4bit;
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ctx->ghash = gcm_ghash_4bit;
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