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arm64: renesas: rzv2l-sr rzg2l-sr device-tree consolidation 

This finishes the cleanup and de-duplication for the rzg2l and rzv2l
implementations of the SolidRun SOMs and Carriers. Essential both SOMs
share identical device-tree with minor changes so move to -common dtsi's
where appropriate for both the SOM and the carriers with only minor
changes in the actual board .dts files.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
This commit is contained in:
Jon Nettleton 2023-12-04 06:02:49 +01:00
parent 0448a54500
commit 9c4f93a7bb
14 changed files with 560 additions and 1608 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
arch/arm64/boot/dts/renesas/rz-hummingboard-common.dtsi
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ Solidrun HummingBoards
*
* Copyright (C) 2023 SolidRun Ltd.
*/
@ -44,6 +44,15 @@
regulator-always-on;
};
reg_sdhi0_vmmc: regulator-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
regulator-always-on;
};
usb0_vbus_otg: regulator-usb0-vbus-otg {
compatible = "regulator-fixed";
regulator-name = "USB0_VBUS_OTG";
@ -254,13 +263,6 @@
};
&pinctrl {
gpio-sd0-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
output-high;
line-name = "gpio_sd0_pwr_en";
};
gpio-lte_on {
gpio-hog;
gpios = <RZG2L_GPIO(17, 0) GPIO_ACTIVE_HIGH>;
@ -274,37 +276,31 @@
output-high;
line-name = "gpio_lte_reset";
};
/*
* The below switch logic can be used to select the device between
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
* HB-Ripple: S3[1] should be at OFF position to enable eMMC
* HB-Ripple: S3[1] should be at position ON to enable uSD card
*/
/*
* TODO: implement device-selection for SolidRun SoM / Carrier
*
* gpio-sd0-dev-sel-hog {
* gpio-hog;
* gpios = <RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
* output-high;
* line-name = "gpio_sd0_dev_sel";
* };
*/
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
//uart-has-rtscts;
status = "okay";
};
/* uSD */
&sdhi0 {
status = "okay";
#if (!SW_SD0_DEV_SEL)
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_sdhi0_vmmc>;
vqmmc-supply = <&reg_sdhi0_vccq>;
sd-uhs-sdr50;
sd-uhs-sdr104;
bus-width = <4>;
max-frequency = <50000000>; /* 50MiB */
status = "disabled";
#endif
cd-gpios = <&pinctrl RZG2L_GPIO(47, 0) GPIO_ACTIVE_LOW>;
};
&spi1 {
@ -312,7 +308,6 @@
pinctrl-names = "default";
dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
dma-names = "tx", "rx";
status = "okay";
};

196
arch/arm64/boot/dts/renesas/rz_2l-sr-pinfunction.dtsi Normal file
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@ -0,0 +1,196 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2L Solidrun SOM pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-names = "default";
gpio-sd0-dev-sel-hog {
gpio-hog;
gpios = <RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_sd0_dev_sel";
};
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
};
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
i2c3_pins: i2c3 {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
qspi0_pins: qspi0 {
qspi0-data {
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
power-source = <1800>;
};
qspi0-ctrl {
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
power-source = <1800>;
};
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
scif2_pins: scif2 {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
};
#if SW_SD0_DEV_SEL
sdhi0_emmc_pins: sd0emmc {
sd0_emmc_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
power-source = <1800>;
};
sd0_emmc_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_emmc_rst {
pins = "SD0_RST#";
power-source = <1800>;
};
};
#else
sdhi0_pins: sd0 {
sd0_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
sd0_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
};
sdhi0_pins_uhs: sd0_uhs {
sd0_data_uhs {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
sd0_ctrl_uhs {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
};
#endif
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
};
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
};
ssi1_pins: ssi1 {
pinmux = <RZG2L_PORT_PINMUX(46, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(46, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(46, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(46, 3, 1)>; /* RXD */
};
};

270
arch/arm64/boot/dts/renesas/rz_2l-sr-som-common.dtsi Normal file
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@ -0,0 +1,270 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source common for the RZ/G2L and RZ/V2L Solidrun SOM
*
* Copyright (C) 2023 SolidRun Ltd.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/mxl-8611x.h>
#include "rz_2l-sr-pinfunction.dtsi"
/ {
aliases {
serial0 = &scif0;
serial1 = &scif1;
serial2 = &scif2;
serial3 = &scif3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c3 = &i2c3;
mmc0 = &sdhi0;
mmc1 = &sdhi1;
ethernet0 = &eth0;
ethernet1 = &eth1;
};
chosen {
stdout-path = "serial0:115200n8";
};
mmngr {
compatible = "renesas,mmngr";
memory-region = <&mmp_reserved>;
};
mmngrbuf {
compatible = "renesas,mmngrbuf";
};
vspm_if {
compatible = "renesas,vspm_if";
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p1v: regulator-vdd-core {
compatible = "regulator-fixed";
regulator-name = "fixed-1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_sdhi0_vccq: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0_VCCQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
states = <3300000 1>, <1800000 0>;
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-always-on;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_LOW>;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "disabled";
renesas,no-ether-link;
phy0: ethernet-phy@0 {
reg = <0>;
mxl-8611x,led0_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_1GB_ON |
MXL8611X_LEDX_CFG_LINK_UP_100MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_10MB_ON
)>;
mxl-8611x,rx-internal-delay-ps = <0>;
mxl-8611x,tx-internal-delay-ps-100m = <2250>;
mxl-8611x,tx-internal-delay-ps-1g = <300>;
};
};
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "disabled";
renesas,no-ether-link;
phy1: ethernet-phy@0 {
reg = <0>;
mxl-8611x,led0_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_1GB_ON |
MXL8611X_LEDX_CFG_LINK_UP_100MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_10MB_ON
)>;
mxl-8611x,rx-internal-delay-ps = <0>;
mxl-8611x,tx-internal-delay-ps-100m = <2250>;
mxl-8611x,tx-internal-delay-ps-1g = <300>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&gpu {
mali-supply = <&reg_1p1v>;
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
/* EEPROM CAT24AA01TDI-GT3 1-kb (128 B x 8) */
eeprom: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
pmic: raa215300@12 {
compatible = "renesas,raa215300";
reg = <0x12>;
rtc-enable;
mpio2-32k-enable;
};
};
&mtu3 {
status = "okay";
};
&ostm1 {
status = "okay";
};
&ostm2 {
status = "okay";
};
&phyrst {
status = "okay";
};
&sbc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "disabled";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_HIGH>;
};
};
#if SW_SD0_DEV_SEL
/* eMMC */
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_sdhi0_vccq>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#endif
/* WiFi - CYW43439 */
&sdhi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
status = "okay";
non-removable;
vmmc-supply = <&reg_3p3v>;
mmc-pwrseq = <&sdio_pwrseq>;
bus-width = <4>;
max-frequency = <50000000>;
fsl,delay-line = <12>;
keep-power-in-suspend;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&wdt0 {
status = "okay";
timeout-sec = <60>;
};
&wdt1 {
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};

184
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-extended.dts
View File

@ -1,186 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ/G2L Solidrun HummingBoard Pro
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2023 SolidRun Ltd.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* DIP-Switch S3 setting on SoM
* 1 : High; 0: Low
* S3[1] : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
*/
#define SW_SD0_DEV_SEL 1
/dts-v1/;
#include "rzg2l-sr-som.dtsi"
#include "rzg2l-sr-pinfunction.dtsi"
/ {
model = "Solidrun RZ/G2L HummingBoard-Extended";
compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "d";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7535_out>;
};
};
};
};
&pinctrl {
gpio-sd0-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
output-high;
line-name = "gpio_sd0_pwr_en";
};
gpio-lte_on {
gpio-hog;
gpios = <RZG2L_GPIO(17, 0) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_lte_on";
};
gpio-lte_reset {
gpio-hog;
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_lte_reset";
};
/*
* The below switch logic can be used to select the device between
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
* HB-Ripple: S3[1] should be at OFF position to enable eMMC
* HB-Ripple: S3[1] should be at position ON to enable uSD card
*/
/*
* TODO: implement device-selection for SolidRun SoM / Carrier
*
* gpio-sd0-dev-sel-hog {
* gpio-hog;
* gpios = <RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
* output-high;
* line-name = "gpio_sd0_dev_sel";
* };
*/
};
&i2c0 {
adv7535@3d {
compatible = "adi,adv7535";
reg = <0x3d>;
adi,dsi-lanes = <4>;
pd-gpios = <&pinctrl RZG2L_GPIO(3, 0) GPIO_ACTIVE_LOW>; // ADV_PD / DSI_EN J9-34 / P4_0
/*
* With interrupts enabled and hdmi connected during boot,
* rzg2l_mipi_dsi_enable never happens and display receives no signal.
* Re-enable once issue has been resolved.
*
* interrupt-parent = <&pinctrl>;
* interrupts = <RZG2L_GPIO(9, 1) IRQ_TYPE_EDGE_FALLING>; // DSI_TS_nINT J5001-43 P9_1
*/
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7535_in: endpoint@0 {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
adv7535_out: endpoint@1 {
remote-endpoint = <&hdmi_con_out>;
};
};
port@2 {
reg = <2>;
codec_endpoint: endpoint {
/* Audio signals not connected. */
};
};
};
};
rtc@69 {
compatible = "abracon,abx80x";
reg = <0x69>;
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
};
eeprom_carrier: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
&dsi0 {
status = "okay";
};
&dsi0_out {
remote-endpoint = <&adv7535_in>;
data-lanes = <1 2 3 4>;
};
&du {
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
//uart-has-rtscts;
status = "okay";
};
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb0_vbus_otg {
gpio = <&pinctrl RZG2L_GPIO(4, 0) GPIO_OPEN_DRAIN>;
gpio-open-drain;
};
&usb1_vbus {
gpio = <&pinctrl RZG2L_GPIO(42, 0) GPIO_OPEN_DRAIN>;
gpio-open-drain;
};
#include "rzg2l-hummingboard-pro.dts"

27
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-pro.dts Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2L Solidrun HummingBoard Pro
*
* Copyright (C) 2023 SolidRun Ltd.
*/
/*
* DIP-Switch S3 setting on SoM
* 1 : High; 0: Low
* S3[1] : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
*/
#define SW_SD0_DEV_SEL 1
/dts-v1/;
#include "rzg2l-sr-som.dtsi"
#include "rz-hummingboard-common.dtsi"
/ {
model = "Solidrun RZ/G2L HummingBoard-Pro";
compatible = "renesas,rzg2l-sr-som", "renesas,r9a07g044l2", "renesas,r9a07g044";
};
&eth1 {
status = "okay";
};

269
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-ripple.dts
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@ -1,13 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ/G2L Solidrun HummingBoard Ripple
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2023 SolidRun Ltd.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* DIP-Switch S3 setting on SoM
* 1 : High; 0: Low
@ -18,268 +15,10 @@
/dts-v1/;
#include "rzg2l-sr-som.dtsi"
#include "rzg2l-sr-pinfunction.dtsi"
#include "rz-hummingboard-common.dtsi"
/ {
model = "Solidrun RZ/G2L HummingBoard-Ripple";
compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
hdmi-out {
compatible = "hdmi-connector";
type = "d";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7535_out>;
};
};
};
cam_ext_2v8: 2p8v {
compatible = "regulator-fixed";
regulator-name = "camera_ext_2v8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
cam_ext_1v8: 1p8v {
compatible = "regulator-fixed";
regulator-name = "camera_ext_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
cam_ext_1v2: 1p2v {
compatible = "regulator-fixed";
regulator-name = "camera_ext_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
imx219_clk: osc25250_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
ar0521_clk: osc27000_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
compatible = "renesas,rzg2l-sr-som", "renesas,r9a07g044l2", "renesas,r9a07g044";
};
&pinctrl {
gpio-sd0-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
output-high;
line-name = "gpio_sd0_pwr_en";
};
gpio-lte_on {
gpio-hog;
gpios = <RZG2L_GPIO(17, 0) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_lte_on";
};
gpio-lte_reset {
gpio-hog;
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_lte_reset";
};
/*
* The below switch logic can be used to select the device between
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
* HB-Ripple: S3[1] should be at OFF position to enable eMMC
* HB-Ripple: S3[1] should be at position ON to enable uSD card
*/
/*
* TODO: implement device-selection for SolidRun SoM / Carrier
*
* gpio-sd0-dev-sel-hog {
* gpio-hog;
* gpios = <RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
* output-high;
* line-name = "gpio_sd0_dev_sel";
* };
*/
};
&i2c0 {
clock-frequency = <400000>;
adv7535@3d {
compatible = "adi,adv7535";
reg = <0x3d>;
adi,dsi-lanes = <4>;
pd-gpios = <&pinctrl RZG2L_GPIO(3, 0) GPIO_ACTIVE_LOW>; // ADV_PD / DSI_EN J9-34 / P4_0
/*
* With interrupts enabled and hdmi connected during boot,
* rzg2l_mipi_dsi_enable never happens and display receives no signal.
* Re-enable once issue has been resolved.
*
* interrupt-parent = <&pinctrl>;
* interrupts = <RZG2L_GPIO(9, 1) IRQ_TYPE_EDGE_FALLING>; // DSI_TS_nINT J5001-43 P9_1
*/
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7535_in: endpoint@0 {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
adv7535_out: endpoint@1 {
remote-endpoint = <&hdmi_con_out>;
};
};
port@2 {
reg = <2>;
codec_endpoint: endpoint {
/* Audio signals not connected. */
};
};
};
};
rtc@69 {
compatible = "abracon,abx80x";
reg = <0x69>;
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
};
eeprom_carrier: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
imx219: sensor@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&imx219_clk>;
clock-names = "extclk";
VANA-supply = <&cam_ext_2v8>;
VDIG-supply = <&cam_ext_1v8>;
VDDL-supply = <&cam_ext_1v2>;
status = "disabled";
port {
imx219_0: endpoint {
remote-endpoint = <&csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <456000000>;
};
};
};
ar0521: sensor@36 {
compatible = "onnn,ar0521";
reg = <0x36>;
clocks = <&ar0521_clk>;
clock-names = "extclk";
vaa-supply = <&cam_ext_2v8>;
vdd-supply = <&cam_ext_1v2>;
vdd_io-supply = <&cam_ext_1v8>;
port {
ar0521_0: endpoint {
remote-endpoint = <&csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
};
};
};
};
&csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
csi2_to_cru: endpoint {
remote-endpoint = <&cru_to_csi2>;
};
};
port@0 {
reg = <0>;
csi2_in: endpoint {
remote-endpoint = <&ar0521_0>;
data-lanes = <1 2 3 4>;
};
};
};
};
&dsi0 {
status = "okay";
};
&dsi0_out {
remote-endpoint = <&adv7535_in>;
data-lanes = <1 2 3 4>;
};
&du {
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
//uart-has-rtscts;
status = "okay";
};
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb0_vbus_otg {
gpio = <&pinctrl RZG2L_GPIO(4, 0) GPIO_OPEN_DRAIN>;
gpio-open-drain;
};
&usb1_vbus {
gpio = <&pinctrl RZG2L_GPIO(42, 0) GPIO_OPEN_DRAIN>;
gpio-open-drain;
};
&eth1 {
status = "disabled";
};

36
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-tutus.dts
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ/G2L SolidRun Tutus Board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
@ -19,11 +19,10 @@
/dts-v1/;
#include "rzg2l-sr-som.dtsi"
#include "rzg2l-sr-pinfunction.dtsi"
/ {
model = "Solidrun RZ/G2L HummingBoard-Tutus";
compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
compatible = "renesas,rzg2l-sr-som","renesas,r9a07g044l2", "renesas,r9a07g044";
x1_clk: x1-clock {
compatible = "fixed-clock";
@ -68,6 +67,27 @@
};
};
usb0_vbus_otg: regulator-usb0-vbus-otg {
compatible = "regulator-fixed";
regulator-name = "USB0_VBUS_OTG";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pinctrl RZG2L_GPIO(4, 0) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
regulator-always-on;
enable-active-high;
};
usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "USB1_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pinctrl RZG2L_GPIO(42, 0) GPIO_ACTIVE_HIGH>;
gpio-open-drain;
regulator-always-on;
enable-active-high;
};
};
&pinctrl {
@ -113,13 +133,3 @@
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb0_vbus_otg {
gpio = <&pinctrl RZG2L_GPIO(4, 0) GPIO_OPEN_DRAIN>;
gpio-open-drain;
};
&usb1_vbus {
gpio = <&pinctrl RZG2L_GPIO(42, 0) GPIO_OPEN_DRAIN>;
gpio-open-drain;
};

106
arch/arm64/boot/dts/renesas/rzg2l-sr-pinfunction.dtsi
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@ -1,106 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
i2c3_pins: i2c3 {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
scif2_pins: scif2 {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
};
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
sd1_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
};
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
};
ssi1_pins: ssi1 {
pinmux = <RZG2L_PORT_PINMUX(46, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(46, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(46, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(46, 3, 1)>; /* RXD */
};
};

512
arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
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@ -1,37 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ/G2L Solidrun SOM
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2023 SolidRun Ltd.
*/
/dts-v1/;
/* RZ/G2L R9A07G044L2 SoC */
#include "r9a07g044l2.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/mxl-8611x.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#include "rz_2l-sr-som-common.dtsi"
/ {
aliases {
serial0 = &scif0;
serial1 = &scif1;
serial2 = &scif2;
serial3 = &scif3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c3 = &i2c3;
mmc0 = &sdhi0;
mmc1 = &sdhi1;
ethernet0 = &eth0;
ethernet1 = &eth1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@ -48,494 +28,12 @@
reusable;
size = <0x0 0x10000000>;
};
mmp_reserved: linux,mmp {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
};
};
mmngr {
compatible = "renesas,mmngr";
memory-region = <&mmp_reserved>;
};
mmngrbuf {
compatible = "renesas,mmngrbuf";
};
vspm_if {
compatible = "renesas,vspm_if";
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p1v: regulator-vdd-core {
compatible = "regulator-fixed";
regulator-name = "fixed-1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
chosen {
stdout-path = "serial0:115200n8";
};
usb0_vbus_otg: regulator-usb0-vbus-otg {
compatible = "regulator-fixed";
regulator-name = "USB0_VBUS_OTG";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pinctrl RZG2L_GPIO(4, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "USB1_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pinctrl RZG2L_GPIO(42, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
};
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
renesas,no-ether-link;
phy0: ethernet-phy@0 {
reg = <0>;
mxl-8611x,led0_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_1GB_ON |
MXL8611X_LEDX_CFG_LINK_UP_100MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_10MB_ON
)>;
mxl-8611x,rx-internal-delay-ps = <0>;
mxl-8611x,tx-internal-delay-ps-100m = <2250>;
mxl-8611x,tx-internal-delay-ps-1g = <300>;
};
};
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
renesas,no-ether-link;
phy1: ethernet-phy@0 {
reg = <0>;
mxl-8611x,led0_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_1GB_ON |
MXL8611X_LEDX_CFG_LINK_UP_100MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_10MB_ON
)>;
mxl-8611x,rx-internal-delay-ps = <0>;
mxl-8611x,tx-internal-delay-ps-100m = <2250>;
mxl-8611x,tx-internal-delay-ps-1g = <300>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&gpu {
mali-supply = <&reg_1p1v>;
memory-region = <&multimedia_cma>;
};
&ostm1 {
status = "okay";
};
&ostm2 {
status = "okay";
};
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
};
qspi0_pins: qspi0 {
qspi0-data {
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
power-source = <1800>;
};
qspi0-ctrl {
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
power-source = <1800>;
};
};
/*
* The switch logic can be used to select the device between
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
*/
/*
* TODO: implement device-selection for SolidRun SoM / Carrier
*
*/
#if SW_SD0_DEV_SEL
/* eMMC */
/* P22_1 - SD0_DEV_SEL (High: [eMMC]; Low: [uSD]) */
gpio-sd0-dev-sel-hog {
gpio-hog;
gpios = <RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_sd0_dev_sel";
};
/* P39_0 - LDO_SEL1 (High: 3.3v [uSD]; Low: 1.8v [eMMC]) */
gpio-sd0-vdd-18v-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 0) GPIO_ACTIVE_LOW>;
output-high;
line-name = "gpio_sd0_vdd_1.8v";
status = "okay";
};
#endif
sdhi0_emmc_pins: sd0emmc {
sd0_emmc_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
power-source = <1800>;
};
sd0_emmc_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_emmc_rst {
pins = "SD0_RST#";
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
sd0_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
sd0_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
sd0_mux {
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
};
};
sdhi0_pins_uhs: sd0_uhs {
sd0_data_uhs {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
sd0_ctrl_uhs {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
};
};
};
&sbc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "disabled";
};
#if (!SW_SD0_DEV_SEL)
/* uSD */
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
sd-uhs-sdr50;
sd-uhs-sdr104;
bus-width = <4>;
max-frequency = <50000000>; /* 50MiB */
status = "okay";
};
#endif
#if SW_SD0_DEV_SEL
/* eMMC */
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#endif
&vccq_sdhi1 {
/* WL_REG_ON (P23_1) */
gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_HIGH>;
};
/* WiFi - CYW43439 */
&sdhi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
status = "okay";
non-removable;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi1>;
bus-width = <4>;
max-frequency = <50000000>;
fsl,delay-line = <12>;
keep-power-in-suspend;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&wdt0 {
status = "okay";
timeout-sec = <60>;
};
&wdt1 {
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};
&canfd {
status = "disabled";
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
&ehci1 {
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
/* EEPROM CAT24AA01TDI-GT3 1-kb (128 B x 8) */
eeprom: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
pmic: raa215300@12 {
compatible = "renesas,raa215300";
reg = <0x12>;
rtc-enable;
mpio2-32k-enable;
};
rtc: isl1208@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
//external-oscillator;
status="disabled";
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
&ohci1 {
status = "okay";
};
&phyrst {
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
pinctrl-names = "default";
max-speed = <115200>;
shutdown-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_HIGH>;
};
};
&spi1 {
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
dma-names = "tx", "rx";
status = "okay";
};
&usb2_phy0 {
vbus-supply = <&usb0_vbus_otg>;
status = "okay";
renesas,no-otg-pins;
};
&usb2_phy1 {
vbus-supply = <&usb1_vbus>;
status = "okay";
};
&du {
status = "okay";
memory-region = <&multimedia_cma>;
};
&dsi0 {
status = "okay";
};
&cru {
status = "okay";
memory-region = <&multimedia_cma>;
};
&mtu3 {
status = "okay";
};

4
arch/arm64/boot/dts/renesas/rzv2l-hummingboard-extended.dts
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ/V2L HummingBoard Pro
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2023 SolidRun Ltd.
*/
#include "rzv2l-hummingboard-pro.dts"

8
arch/arm64/boot/dts/renesas/rzv2l-hummingboard-pro.dts
View File

@ -1,13 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ/V2L SolidRun HummingBoard Pro
*
* Copyright (C) 2021 Renesas Electronics Corp.
* Copyright (C) 2023 SolidRun Ltd.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* DIP-Switch S3 setting on SoM
* 1 : High; 0: Low
@ -19,7 +16,6 @@
/dts-v1/;
#include "rzv2l-sr-som.dtsi"
#include "rz-hummingboard-common.dtsi"
#include "rzv2l-sr-pinfunction.dtsi"
/ {
model = "Solidrun RZ/V2L HummingBoard-Pro";

3
arch/arm64/boot/dts/renesas/rzv2l-hummingboard-ripple.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2LC Solidrun SOM
* Device Tree Source for the RZ/V2L Solidrun HummingBoard Ripple
*
* Copyright (C) 2023 SolidRun Ltd.
*/
@ -16,7 +16,6 @@
/dts-v1/;
#include "rzv2l-sr-som.dtsi"
#include "rz-hummingboard-common.dtsi"
#include "rzv2l-sr-pinfunction.dtsi"
/ {
model = "Solidrun RZ/V2L HummingBoard-Ripple";

106
arch/arm64/boot/dts/renesas/rzv2l-sr-pinfunction.dtsi
View File

@ -1,106 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2L Solidrun SOM pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
&pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
i2c3_pins: i2c3 {
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
scif1_pins: scif1 {
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
};
scif2_pins: scif2 {
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
};
sdhi1_pins: sd1 {
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
power-source = <3300>;
};
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sdhi1_pins_uhs: sd1_uhs {
sd1_data_uhs {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
power-source = <1800>;
};
sd1_ctrl_uhs {
pins = "SD1_CLK", "SD1_CMD";
power-source = <1800>;
};
sd1_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
};
};
sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
};
ssi0_pins: ssi0 {
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
};
ssi1_pins: ssi1 {
pinmux = <RZG2L_PORT_PINMUX(46, 0, 1)>, /* BCK */
<RZG2L_PORT_PINMUX(46, 1, 1)>, /* RCK */
<RZG2L_PORT_PINMUX(46, 2, 1)>, /* TXD */
<RZG2L_PORT_PINMUX(46, 3, 1)>; /* RXD */
};
};

392
arch/arm64/boot/dts/renesas/rzv2l-sr-som.dtsi
View File

@ -6,32 +6,13 @@
*/
/dts-v1/;
/* RZ/V2L R9A07G054L2 SoC */
#include "r9a07g054l2.dtsi"
#include "rz_2l-sr-som-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/mxl-8611x.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
aliases {
serial0 = &scif0;
serial1 = &scif1;
serial2 = &scif2;
serial3 = &scif3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c3 = &i2c3;
mmc0 = &sdhi0;
mmc1 = &sdhi1;
ethernet0 = &eth0;
ethernet1 = &eth1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@ -73,374 +54,5 @@
reg = <0x0 0xB4000000 0x0 0x03000000>;
};
};
mmngr {
compatible = "renesas,mmngr";
memory-region = <&mmp_reserved>;
};
mmngrbuf {
compatible = "renesas,mmngrbuf";
};
vspm_if {
compatible = "renesas,vspm_if";
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p1v: regulator-vdd-core {
compatible = "regulator-fixed";
regulator-name = "fixed-1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_LOW>;
};
};
&eth0 {
pinctrl-0 = <&eth0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "disabled";
renesas,no-ether-link;
phy0: ethernet-phy@0 {
reg = <0>;
mxl-8611x,led0_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_1GB_ON |
MXL8611X_LEDX_CFG_LINK_UP_100MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_10MB_ON
)>;
mxl-8611x,rx-internal-delay-ps = <0>;
mxl-8611x,tx-internal-delay-ps-100m = <2250>;
mxl-8611x,tx-internal-delay-ps-1g = <300>;
};
};
&eth1 {
pinctrl-0 = <&eth1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "disabled";
renesas,no-ether-link;
phy1: ethernet-phy@0 {
reg = <0>;
mxl-8611x,led0_cfg = <(
MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON |
MXL8611X_LEDX_CFG_LINK_UP_1GB_ON |
MXL8611X_LEDX_CFG_LINK_UP_100MB_ON |
MXL8611X_LEDX_CFG_LINK_UP_10MB_ON
)>;
mxl-8611x,rx-internal-delay-ps = <0>;
mxl-8611x,tx-internal-delay-ps-100m = <2250>;
mxl-8611x,tx-internal-delay-ps-1g = <300>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&gpu {
mali-supply = <&reg_1p1v>;
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
/* EEPROM CAT24AA01TDI-GT3 1-kb (128 B x 8) */
eeprom: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
pmic: raa215300@12 {
compatible = "renesas,raa215300";
reg = <0x12>;
rtc-enable;
mpio2-32k-enable;
};
};
&mtu3 {
status = "okay";
};
&ostm1 {
status = "okay";
};
&ostm2 {
status = "okay";
};
&phyrst {
status = "okay";
};
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
};
qspi0_pins: qspi0 {
qspi0-data {
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
power-source = <1800>;
};
qspi0-ctrl {
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
power-source = <1800>;
};
};
/*
* The switch logic can be used to select the device between
* eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
*/
/*
* TODO: implement device-selection for SolidRun SoM / Carrier
*
*/
#if SW_SD0_DEV_SEL
/* eMMC */
/* P22_1 - SD0_DEV_SEL (High: [eMMC]; Low: [uSD]) */
gpio-sd0-dev-sel-hog {
gpio-hog;
gpios = <RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio_sd0_dev_sel";
};
/* P39_0 - LDO_SEL1 (High: 3.3v [uSD]; Low: 1.8v [eMMC]) */
gpio-sd0-vdd-18v-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 0) GPIO_ACTIVE_LOW>;
output-high;
line-name = "gpio_sd0_vdd_1.8v";
status = "okay";
};
#endif
sdhi0_emmc_pins: sd0emmc {
sd0_emmc_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
power-source = <1800>;
};
sd0_emmc_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_emmc_rst {
pins = "SD0_RST#";
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
sd0_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
sd0_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
sd0_mux {
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
};
};
sdhi0_pins_uhs: sd0_uhs {
sd0_data_uhs {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
sd0_ctrl_uhs {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
};
};
};
&sbc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "disabled";
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_HIGH>;
};
};
#if (!SW_SD0_DEV_SEL)
/* uSD */
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
sd-uhs-sdr50;
sd-uhs-sdr104;
bus-width = <4>;
max-frequency = <50000000>; /* 50MiB */
status = "disabled";
};
#endif
#if SW_SD0_DEV_SEL
/* eMMC */
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#endif
/* WiFi - CYW43439 */
&sdhi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
status = "okay";
non-removable;
vmmc-supply = <&reg_3p3v>;
mmc-pwrseq = <&sdio_pwrseq>;
bus-width = <4>;
max-frequency = <50000000>;
fsl,delay-line = <12>;
keep-power-in-suspend;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&wdt0 {
status = "okay";
timeout-sec = <60>;
};
&wdt1 {
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};