From 0e699d9e4818e32c04bc338c43fb66fb7a0ecc8e Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sun, 14 Apr 2024 17:15:41 +0200 Subject: [PATCH] u-boot: improve compatibility with pci devices behind bridges --- ...ighest-subordinate-bus-number-for-br.patch | 34 ++++++++++ ...ait-100ms-for-Link-Up-in-ls_pcie_g4_.patch | 65 +++++++++++++++++++ ...t-100ms-for-Link-Up-in-ls_pcie_probe.patch | 59 +++++++++++++++++ 3 files changed, 158 insertions(+) create mode 100644 patches/u-boot-LSDK-21.08/0050-pci-Update-the-highest-subordinate-bus-number-for-br.patch create mode 100644 patches/u-boot-LSDK-21.08/0051-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch create mode 100644 patches/u-boot-LSDK-21.08/0052-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch diff --git a/patches/u-boot-LSDK-21.08/0050-pci-Update-the-highest-subordinate-bus-number-for-br.patch b/patches/u-boot-LSDK-21.08/0050-pci-Update-the-highest-subordinate-bus-number-for-br.patch new file mode 100644 index 0000000..6c34da4 --- /dev/null +++ b/patches/u-boot-LSDK-21.08/0050-pci-Update-the-highest-subordinate-bus-number-for-br.patch @@ -0,0 +1,34 @@ +From 1742cdc4202d873af30ae3e4d3879092a7aead07 Mon Sep 17 00:00:00 2001 +From: Masami Hiramatsu +Date: Fri, 16 Apr 2021 14:53:46 -0700 +Subject: [PATCH 50/52] pci: Update the highest subordinate bus number for + bridge setup + +Update the highest subordinate bus number after probing the devices +under the bus for setting up the bridge correctly. +The commit 42f3663a3f67 ("pci: Update to use new sequence numbers") +removed this but it is required if a PCIe bridge is under the bus. + +Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers") +Signed-off-by: Masami Hiramatsu +--- + drivers/pci/pci-uclass.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c +index dfd54b339f..f463ef3550 100644 +--- a/drivers/pci/pci-uclass.c ++++ b/drivers/pci/pci-uclass.c +@@ -646,6 +646,9 @@ int dm_pci_hose_probe_bus(struct udevice *bus) + return log_msg_ret("probe", ret); + } + ++ if (!ea_pos) ++ sub_bus = pci_get_bus_max(); ++ + dm_pciauto_postscan_setup_bridge(bus, sub_bus); + + return sub_bus; +-- +2.35.3 + diff --git a/patches/u-boot-LSDK-21.08/0051-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch b/patches/u-boot-LSDK-21.08/0051-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch new file mode 100644 index 0000000..7dd51e5 --- /dev/null +++ b/patches/u-boot-LSDK-21.08/0051-pci-ls_pcie_g4-Wait-100ms-for-Link-Up-in-ls_pcie_g4_.patch @@ -0,0 +1,65 @@ +From 407e2364798f2f1714097a8efef08779f20d5c22 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Wed, 3 Apr 2024 17:58:37 +0200 +Subject: [PATCH 51/52] pci: ls_pcie_g4: Wait 100ms for Link Up in + ls_pcie_g4_probe + +PCI Link-up can be delayed especially with pci bridges or fpga starting +up slowly. + +Add a 100ms delay during probe polling for link-up. + +Signed-off-by: Josua Mayer +--- + drivers/pci/pcie_layerscape_gen4.c | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c +index 255e73181d..9fe95268c4 100644 +--- a/drivers/pci/pcie_layerscape_gen4.c ++++ b/drivers/pci/pcie_layerscape_gen4.c +@@ -19,6 +19,9 @@ + + #include "pcie_layerscape_gen4.h" + ++#define LINK_WAIT_RETRIES 100 ++#define LINK_WAIT_TIMEOUT 1000 ++ + DECLARE_GLOBAL_DATA_PTR; + + LIST_HEAD(ls_pcie_g4_list); +@@ -50,6 +53,22 @@ static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie) + return 1; + } + ++static int ls_pcie_g4_wait_for_link(struct ls_pcie_g4 *pcie) ++{ ++ int retries; ++ ++ /* check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) { ++ if (ls_pcie_g4_link_up(pcie)) { ++ return 1; ++ } ++ ++ udelay(LINK_WAIT_TIMEOUT); ++ } ++ ++ return 0; ++} ++ + static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie) + { + ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY); +@@ -550,7 +569,7 @@ static int ls_pcie_g4_probe(struct udevice *dev) + val |= PPIO_EN; + ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val); + +- if (!ls_pcie_g4_link_up(pcie)) { ++ if (!ls_pcie_g4_wait_for_link(pcie)) { + /* Let the user know there's no PCIe link */ + printf(": no link\n"); + return 0; +-- +2.35.3 + diff --git a/patches/u-boot-LSDK-21.08/0052-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch b/patches/u-boot-LSDK-21.08/0052-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch new file mode 100644 index 0000000..beec516 --- /dev/null +++ b/patches/u-boot-LSDK-21.08/0052-pci-ls_pcie-Wait-100ms-for-Link-Up-in-ls_pcie_probe.patch @@ -0,0 +1,59 @@ +From abada4616a827b556d2a4aa30533fa455c1cba81 Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 14 Apr 2024 16:45:42 +0200 +Subject: [PATCH 52/52] pci: ls_pcie: Wait 100ms for Link Up in ls_pcie_probe + +PCI Link-up can be delayed especially with pci bridges or fpga starting +up slowly. + +Add a 100ms delay during probe polling for link-up. + +Signed-off-by: Josua Mayer +--- + drivers/pci/pcie_layerscape_rc.c | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c +index bd2c19f7f0..5f65667577 100644 +--- a/drivers/pci/pcie_layerscape_rc.c ++++ b/drivers/pci/pcie_layerscape_rc.c +@@ -19,8 +19,27 @@ + #endif + #include "pcie_layerscape.h" + ++#define LINK_WAIT_RETRIES 100 ++#define LINK_WAIT_TIMEOUT 1000 ++ + DECLARE_GLOBAL_DATA_PTR; + ++static int ls_pcie_wait_for_link(struct ls_pcie *pcie) ++{ ++ int retries; ++ ++ /* check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) { ++ if (ls_pcie_link_up(pcie)) { ++ return 1; ++ } ++ ++ udelay(LINK_WAIT_TIMEOUT); ++ } ++ ++ return 0; ++} ++ + static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev) + { + struct ls_pcie *pcie = pcie_rc->pcie; +@@ -354,7 +373,7 @@ static int ls_pcie_probe(struct udevice *dev) + "Root Complex"); + ls_pcie_setup_ctrl(pcie_rc); + +- if (!ls_pcie_link_up(pcie)) { ++ if (!ls_pcie_wait_for_link(pcie)) { + /* Let the user know there's no PCIe link */ + printf(": no link\n"); + return 0; +-- +2.35.3 +