lx2162-clearfog: add support for 25Gbps on 2x SFP+ connectors
Ensure to choose serdes 1 protocol 18 to enable support for 25Gbpps on 2 of the SFP+ connectors. The other 2 do not have a retimer and will likely have bad signal integrity if used at 25Gbpbs.
This commit is contained in:
parent
7fbc7465e0
commit
7d929bd639
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@ -85,3 +85,4 @@ CONFIG_IPVLAN=y
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CONFIG_CGROUPS=y
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CONFIG_NAMESPACES=y
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CONFIG_NET_NS=y
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CONFIG_PHY_DS250DFX10=y
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@ -0,0 +1,424 @@
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From 7fe34a8f3c05b7ffef115dfab90afd4e124299b6 Mon Sep 17 00:00:00 2001
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From: Josua Mayer <josua@solid-run.com>
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Date: Wed, 12 Oct 2022 18:46:09 +0300
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Subject: [PATCH 62/63] net: phy: create driver for ds250df4x10 retimer
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Create driver for the TI DS250DF410 and DS250DF810 retimers.
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Both variants feature either 4 or 8 channels to be configured
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individually from 20.2752 to 25.8Gbps, while also supporting subrates by
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dividing either with 2 or 4.
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Configuration is provided to other drivers by implementing a generic phy
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with support for set_mode.
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For now only 2 of the standard configurations are supported, to support
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10 & 25Gbps ethernet modes:
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- PHY_INTERFACE_MODE_10GBASER: 10.3125Gbps
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- PHY_INTERFACE_MODE_25GBASER: 25.78125Gbps
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The driver also hardcodes signal conditioning parameters.
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Future revisions shall read those from device-tree instead.
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Signed-off-by: Josua Mayer <josua@solid-run.com>
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---
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drivers/phy/ti/Kconfig | 9 +
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drivers/phy/ti/Makefile | 1 +
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drivers/phy/ti/phy-ti-ds250dfx10.c | 354 +++++++++++++++++++++++++++++
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3 files changed, 364 insertions(+)
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create mode 100644 drivers/phy/ti/phy-ti-ds250dfx10.c
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diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig
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index 15a3bcf32308..7117e819cdfd 100644
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--- a/drivers/phy/ti/Kconfig
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+++ b/drivers/phy/ti/Kconfig
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@@ -84,6 +84,15 @@ config TI_PIPE3
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This driver interacts with the "OMAP Control PHY Driver" to power
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on/off the PHY.
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+config PHY_DS250DFX10
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+ tristate "Texas Instruments DS250DFX10 Retimer"
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+ depends on OF
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+ select GENERIC_PHY
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+ help
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+ Enable to support runtime configuration of DS250DFX10 retimers.
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+ The retimers are modeled as generic PHYs,
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+ currently supporting 10 & 25 GBASER link speeds.
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+
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config PHY_TUSB1210
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tristate "TI TUSB1210 ULPI PHY module"
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depends on USB_ULPI_BUS
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diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile
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index dcba2571c9bd..718db2aadcdd 100644
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--- a/drivers/phy/ti/Makefile
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+++ b/drivers/phy/ti/Makefile
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@@ -4,6 +4,7 @@ obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
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obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
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obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
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obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
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+obj-$(CONFIG_PHY_DS250DFX10) += phy-ti-ds250dfx10.o
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obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
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obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
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obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o
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diff --git a/drivers/phy/ti/phy-ti-ds250dfx10.c b/drivers/phy/ti/phy-ti-ds250dfx10.c
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new file mode 100644
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index 000000000000..bfbbf35c430c
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--- /dev/null
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+++ b/drivers/phy/ti/phy-ti-ds250dfx10.c
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@@ -0,0 +1,354 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Driver for the TI DS250DF410 Retimer
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+ *
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+ * Copyright (C) 2022-2023 Josua Mayer <josua@solid-run.com>
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+ */
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+
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+#include <linux/i2c.h>
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+#include <linux/module.h>
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+#include <linux/phy.h>
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+#include <linux/phy/phy.h>
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+
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+#define DS250DF410_REG_CHAN_CONFIG_ID 0xEF
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+#define DS250DF410_MASK_CHAN_CONFIG_ID GENMASK(3, 0)
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+#define DS250DF410_REG_VERSION 0xF0
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+#define DS250DF410_REG_DEVICE_ID 0xF1
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+#define DS250DF410_REG_CHAN_VERSION 0xF3
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+#define DS250DF410_MASK_CHAN_VERSION GENMASK(7, 4)
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+#define DS250DF410_MASK_SHARE_VERSION GENMASK(3, 0)
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+
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+struct ds250dfx10_phy_priv {
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+ struct i2c_client *client;
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+ uint8_t channel;
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+};
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+
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+struct ds250dfx10_priv {
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+ struct phy *phy[8];
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+ struct phy_provider *provider;
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+};
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+
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+static int ds250dfx10_read_register(struct i2c_client *client, uint8_t address, uint8_t *value,
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+ uint8_t mask)
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+{
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+ s32 res;
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+
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+ res = i2c_smbus_read_byte_data(client, address);
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+ if (res < 0) {
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+ dev_err(&client->dev, "failed to read register %#04x: %d\n", address,
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+ res);
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+ return -EIO;
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+ }
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+
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+ *value = res & mask;
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+ return 0;
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+}
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+
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+static int ds250dfx10_write_register(struct i2c_client *client, uint8_t address, uint8_t value,
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+ uint8_t mask)
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+{
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+ int ret;
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+ uint8_t tmp;
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+ s32 res;
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+
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+ // combine with current value according to mask
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+ if (mask != 0xFF) {
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+ ret = ds250dfx10_read_register(client, address, &tmp, ~mask);
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+ if (ret)
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+ return ret;
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+
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+ value = (value & mask) | tmp;
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+ }
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+
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+ // write new value
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+ res = i2c_smbus_write_byte_data(client, address, value);
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+ if (res < 0) {
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+ dev_err(&client->dev, "failed to write register %#04x=%#04x: %d\n",
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+ address, value, res);
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+ return -EIO;
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+ }
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+
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+ return 0;
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+}
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+
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+static void ds250dfx10_config_10g(struct i2c_client *client, uint8_t channel)
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+{
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+ int ret = 0;
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+
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+ // enable smbus access to single channel
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+ ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03);
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+
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+ // select channel
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+ ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF);
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+
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+ // reset channel registers
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+ ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04);
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+
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+ // assert cdr
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+ ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
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+
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+ // select 10.3125 rate
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+ ret |= ds250dfx10_write_register(client, 0x2F, 0x00, 0xF0);
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+
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+ // enable pre- and post-fir
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+ ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80);
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+
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+ // set main cursor magnitude +15
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+ ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40);
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+ ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F);
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+
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+ // set pre cursor magnitude -4
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+ ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40);
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+ ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F);
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+
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+ // set post cursor magnitude -4
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+ ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40);
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+ ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F);
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+
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+ // deassert cdr
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+ ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C);
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+
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+ if (!ret)
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+ dev_info(&client->dev, "configured channel %u for 10G\n", channel);
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+}
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+
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+static void ds250dfx10_config_25g(struct i2c_client *client, uint8_t channel)
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+{
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+ int ret = 0;
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+
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+ // enable smbus access to single channel
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+ ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03);
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+
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+ // select channel
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+ ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF);
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+
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+ // reset channel registers
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+ ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04);
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+
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+ // assert cdr
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+ ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
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+
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+ // select 25.78125 rate
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+ ret |= ds250dfx10_write_register(client, 0x2F, 0x50, 0xF0);
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+
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+ // enable pre- and post-fir
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+ ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80);
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+
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+ // set main cursor magnitude +15
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+ ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40);
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+ ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F);
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+
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+ // set pre cursor magnitude -4
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+ ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40);
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+ ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F);
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+
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+ // set post cursor magnitude -4
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+ ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40);
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+ ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F);
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+
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+ // deassert cdr
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+ ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C);
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+
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+ if (!ret)
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+ dev_info(&client->dev, "configured channel %u for 25G\n", channel);
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+}
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+
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+static int ds250dfx10_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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+{
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+ struct ds250dfx10_phy_priv *priv = phy_get_drvdata(phy);
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+
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+ if (mode != PHY_MODE_ETHERNET)
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+ return -EOPNOTSUPP;
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+
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+ switch (submode) {
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ ds250dfx10_config_10g(priv->client, priv->channel);
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+ break;
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+ case PHY_INTERFACE_MODE_25GBASER:
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+ ds250dfx10_config_25g(priv->client, priv->channel);
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+ break;
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+ default:
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+ dev_err(&priv->client->dev, "unsupported interface submode %i\n",
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+ submode);
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+ return -EOPNOTSUPP;
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct phy_ops ds250dfx10_phy_ops = {
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+ .set_mode = ds250dfx10_phy_set_mode,
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+ .owner = THIS_MODULE,
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+};
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+
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+static struct phy *ds250dfx10_of_xlate(struct device *dev, struct of_phandle_args *args)
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+{
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+ struct ds250dfx10_priv *phy_priv = dev_get_drvdata(dev);
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+ int channel;
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+
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+ if (args->args_count != 1) {
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+ dev_err(phy_priv->provider->dev, "DT did not pass correct no of args\n");
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+ return ERR_PTR(-ENODEV);
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+ }
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+
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+ channel = args->args[0];
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+ if (WARN_ON(channel >= ARRAY_SIZE(phy_priv->phy))
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+ || !phy_priv->phy[channel])
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+ return ERR_PTR(-ENODEV);
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+
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+ return phy_priv->phy[channel];
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+}
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+
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+static int ds250dfx10_probe(struct i2c_client *client)
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+{
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+ struct ds250dfx10_priv *priv;
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+ struct ds250dfx10_phy_priv *phy_priv;
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+ struct device_node *child;
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+ uint8_t chan_config_id, device_id, version, chan_version, share_version, channels;
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+ uint8_t reg;
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+ int ret, i;
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+
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+ priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv) {
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+ ret = -ENOMEM;
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+ goto no_phys;
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+ }
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+ i2c_set_clientdata(client, priv);
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+
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+ /* read device identification */
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+ ret = ds250dfx10_read_register(client, DS250DF410_REG_DEVICE_ID, ®, 0xFF);
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+ if (ret)
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+ goto no_phys;
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+ device_id = reg;
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+
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+ /* read device version */
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+ ret = ds250dfx10_read_register(client, DS250DF410_REG_VERSION, ®, 0xFF);
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+ if (ret)
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+ goto no_phys;
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+ version = reg;
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+
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+ // report device id
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+ dev_info(&client->dev, "device id %#04x version %#04x\n", device_id, version);
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+
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+ switch (device_id) {
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+ case 0x10:
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+ break;
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+ default:
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+ dev_warn(&client->dev, "unknown device id, expect problems!\n");
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+ }
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+
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+ // read channel config id
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+ ret = ds250dfx10_read_register(client, DS250DF410_REG_CHAN_CONFIG_ID, ®,
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+ DS250DF410_MASK_CHAN_CONFIG_ID);
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+ if (ret)
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+ goto no_phys;
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+ chan_config_id = reg;
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+
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+ switch (chan_config_id) {
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+ case 0xC:
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+ channels = 8;
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+ break;
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+ case 0xE:
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+ channels = 4;
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+ break;
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+ default:
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+ dev_err(&client->dev, "unknown channel configuration id %#03x\n", chan_config_id);
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+ ret = -EINVAL;
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+ goto no_phys;
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+ }
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+ dev_info(&client->dev, "%u channels\n", channels);
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+
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+ // read channel version
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+ ret = ds250dfx10_read_register(client, DS250DF410_REG_CHAN_VERSION, ®, 0xFF);
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+ if (ret)
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+ goto no_phys;
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+ chan_version = (reg & DS250DF410_MASK_CHAN_VERSION) >> 4;
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+ share_version = reg & DS250DF410_MASK_SHARE_VERSION;
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+
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+ dev_info(&client->dev, "channel version %#03x share version %#03x\n",
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+ chan_version, share_version);
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+
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+ // create PHY objects for all channels
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+ for (i = 0; i < channels; i++) {
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+ priv->phy[i] = devm_phy_create(&client->dev, child, &ds250dfx10_phy_ops);
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+ if (IS_ERR(priv->phy[i])) {
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+ ret = PTR_ERR(priv->phy[i]);
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+ priv->phy[i] = NULL;
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+ of_node_put(child);
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+ goto no_provider;
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+ }
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+
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+ phy_priv = devm_kzalloc(&client->dev, sizeof(*phy_priv), GFP_KERNEL);
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+ if (!phy_priv) {
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+ ret = -ENOMEM;
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+ goto no_provider;
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+ }
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+ phy_set_drvdata(priv->phy[i], phy_priv);
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+
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+ phy_priv->client = client;
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+ phy_priv->channel = i;
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+
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+ dev_info(&client->dev, "created phy for channel %u\n", i);
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+ }
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+ of_node_put(child);
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+
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+ // register self as phy provider with generic lookup function
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+ priv->provider = devm_of_phy_provider_register(&client->dev, ds250dfx10_of_xlate);
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+
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+ return 0;
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+
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+ devm_of_phy_provider_unregister(&client->dev, priv->provider);
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+no_provider:
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+ for (i = 0; i < 8; i++) {
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+ if (priv->phy[i])
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+ devm_phy_destroy(&client->dev, priv->phy[i]);
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+ }
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+no_phys:
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+ return ret;
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+}
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+
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+static int ds250dfx10_remove(struct i2c_client *client)
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+{
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+ struct ds250dfx10_priv *priv = i2c_get_clientdata(client);
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+ int i;
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+
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+ for (i = 0; i < 8; i++)
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+ if (priv->phy[i])
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+ devm_phy_destroy(&client->dev, priv->phy[i]);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_OF
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+static const struct of_device_id ds250dfx10_dt_ids[] = {
|
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+ { .compatible = "ti,ds250df410", },
|
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+ { .compatible = "ti,ds250df810", },
|
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+ { }
|
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+};
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+MODULE_DEVICE_TABLE(of, ds250dfx10_dt_ids);
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+#endif
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+
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+static struct i2c_device_id ds250dfx10_idtable[] = {
|
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+ { "ds250df410", 0 },
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+ { "ds250df810", 1 },
|
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+ { }
|
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+};
|
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+
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+MODULE_DEVICE_TABLE(i2c, ds250dfx10_idtable);
|
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+
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+static struct i2c_driver ds250dfx10_driver = {
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+ .driver = {
|
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+ .name = "ds250dfx10",
|
||||
+ .of_match_table = of_match_ptr(ds250dfx10_dt_ids),
|
||||
+ },
|
||||
+
|
||||
+ .id_table = ds250dfx10_idtable,
|
||||
+ .probe_new = ds250dfx10_probe,
|
||||
+ .remove = ds250dfx10_remove,
|
||||
+};
|
||||
+
|
||||
+module_i2c_driver(ds250dfx10_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("Josua Mayer <josua@solid-run.com>");
|
||||
+MODULE_DESCRIPTION("TI DS250DFX10 Retimer Driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--
|
||||
2.35.3
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
From f54f49af359f8208f2ba1780ec6ac8ef587310c9 Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Sun, 16 Apr 2023 13:24:31 +0300
|
||||
Subject: [PATCH 63/63] arm64: dts: lx2162-clearfog: add description for
|
||||
retimer
|
||||
|
||||
LX2162 Clearfog has a retimer on 2x SFP+ connectors.
|
||||
Add a node for the retimer and link it to the appropriate mac nodes.
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
.../dts/freescale/fsl-lx2162a-clearfog.dts | 20 +++++++++++++++----
|
||||
1 file changed, 16 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
|
||||
index 961c9a6dac0f..25975bb64f12 100644
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
|
||||
@@ -75,9 +75,10 @@ sfp_bb: sfp-bb {
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
- retimer@30 {
|
||||
+ retimer: ds250df410@18 {
|
||||
compatible = "ti,ds250df410";
|
||||
- reg = <0x30>;
|
||||
+ reg = <0x18>;
|
||||
+ #phy-cells = <1>;
|
||||
};
|
||||
|
||||
i2c-switch@70 {
|
||||
@@ -191,6 +192,7 @@ pcieclk@6b {
|
||||
&dpmac3 {
|
||||
status = "okay";
|
||||
phys = <&serdes_1 7>;
|
||||
+ phy-names = "serdes";
|
||||
managed = "in-band-status";
|
||||
sfp = <&sfp_at>;
|
||||
link-status-led = <&led_sfp_at>;
|
||||
@@ -204,6 +206,7 @@ &pcs_mdio3 {
|
||||
&dpmac4 {
|
||||
status = "okay";
|
||||
phys = <&serdes_1 6>;
|
||||
+ phy-names = "serdes";
|
||||
managed = "in-band-status";
|
||||
sfp = <&sfp_ab>;
|
||||
link-status-led = <&led_sfp_ab>;
|
||||
@@ -215,7 +218,8 @@ &pcs_mdio4 {
|
||||
|
||||
&dpmac5 {
|
||||
status = "okay";
|
||||
- phys = <&serdes_1 5>;
|
||||
+ phys = <&serdes_1 5>, <&retimer 2>, <&retimer 3>;
|
||||
+ phy-names = "serdes", "retimer", "retimer";
|
||||
managed = "in-band-status";
|
||||
sfp = <&sfp_bt>;
|
||||
link-status-led = <&led_sfp_bt>;
|
||||
@@ -227,7 +231,8 @@ &pcs_mdio5 {
|
||||
|
||||
&dpmac6 {
|
||||
status = "okay";
|
||||
- phys = <&serdes_1 4>;
|
||||
+ phys = <&serdes_1 4>, <&retimer 0>, <&retimer 1>;
|
||||
+ phy-names = "serdes", "retimer", "retimer";
|
||||
managed = "in-band-status";
|
||||
sfp = <&sfp_bb>;
|
||||
link-status-led = <&led_sfp_bb>;
|
||||
@@ -300,6 +305,7 @@ &pcs_mdio11 {
|
||||
&dpmac12 {
|
||||
status = "okay";
|
||||
phys = <&serdes_2 1>;
|
||||
+ phy-names = "serdes";
|
||||
phy-handle = <ðernet_phy0>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
@@ -315,6 +321,7 @@ &dpmac17 {
|
||||
|
||||
status = "okay";
|
||||
phys = <&serdes_2 2>;
|
||||
+ phy-names = "serdes";
|
||||
phy-handle = <ðernet_phy4>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
@@ -326,6 +333,7 @@ &pcs_mdio17 {
|
||||
&dpmac18 {
|
||||
status = "okay";
|
||||
phys = <&serdes_2 3>;
|
||||
+ phy-names = "serdes";
|
||||
phy-handle = <ðernet_phy6>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
@@ -337,6 +345,7 @@ &pcs_mdio18 {
|
||||
&dpmac15 {
|
||||
status = "okay";
|
||||
phys = <&serdes_2 4>;
|
||||
+ phy-names = "serdes";
|
||||
phy-handle = <ðernet_phy3>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
@@ -348,6 +357,7 @@ &pcs_mdio15 {
|
||||
&dpmac16 {
|
||||
status = "okay";
|
||||
phys = <&serdes_2 5>;
|
||||
+ phy-names = "serdes";
|
||||
phy-handle = <ðernet_phy1>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
@@ -359,6 +369,7 @@ &pcs_mdio16 {
|
||||
&dpmac13 {
|
||||
status = "okay";
|
||||
phys = <&serdes_2 6>;
|
||||
+ phy-names = "serdes";
|
||||
phy-handle = <ðernet_phy5>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
@@ -370,6 +381,7 @@ &pcs_mdio13 {
|
||||
&dpmac14 {
|
||||
status = "okay";
|
||||
phys = <&serdes_2 7>;
|
||||
+ phy-names = "serdes";
|
||||
phy-handle = <ðernet_phy7>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
--
|
||||
2.35.3
|
||||
|
8
runme.sh
8
runme.sh
|
@ -152,11 +152,19 @@ case "${SERDES}" in
|
|||
DPC=LX2162-USOM/clearfog-s1_3-s2_0-dpc.dtb
|
||||
DPL=LX2162-USOM/clearfog-s1_3-s2_0-dpl.dtb
|
||||
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
|
||||
MC_FORCE=patches/mc_lx2160a_10.32.0.itb
|
||||
;;
|
||||
LX2162A_CLEARFOG_3_9_*)
|
||||
DPC=LX2162-USOM/clearfog-s1_3-s2_9-dpc.dtb
|
||||
DPL=LX2162-USOM/clearfog-s1_3-s2_9-dpl.dtb
|
||||
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
|
||||
MC_FORCE=patches/mc_lx2160a_10.32.0.itb
|
||||
;;
|
||||
LX2162A_CLEARFOG_18_0_*)
|
||||
DPC=LX2162-USOM/clearfog-s1_3-s2_0-dpc.dtb
|
||||
DPL=LX2162-USOM/clearfog-s1_3-s2_0-dpl.dtb
|
||||
DEFAULT_FDT_FILE="fsl-lx2162a-clearfog.dtb"
|
||||
MC_FORCE=patches/mc_lx2160a_10.36.100.itb
|
||||
;;
|
||||
*)
|
||||
echo "Please define SERDES configuration"
|
||||
|
|
Loading…
Reference in New Issue