193 lines
6.1 KiB
Rust
193 lines
6.1 KiB
Rust
//! Prevent false sharing by padding and aligning to the length of a cache line.
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//!
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//! In concurrent programming, sometimes it is desirable to make sure commonly accessed shared data
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//! is not all placed into the same cache line. Updating an atomic value invalidates the whole cache
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//! line it belongs to, which makes the next access to the same cache line slower for other CPU
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//! cores. Use [`CachePadded`] to ensure updating one piece of data doesn't invalidate other cached
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//! data.
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//!
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//! # Size and alignment
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//!
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//! Cache lines are assumed to be N bytes long, depending on the architecture:
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//!
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//! * On x86-64, aarch64, and powerpc64, N = 128.
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//! * On arm, mips, mips64, and riscv64, N = 32.
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//! * On s390x, N = 256.
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//! * On all others, N = 64.
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//!
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//! Note that N is just a reasonable guess and is not guaranteed to match the actual cache line
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//! length of the machine the program is running on.
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//!
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//! The size of `CachePadded<T>` is the smallest multiple of N bytes large enough to accommodate
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//! a value of type `T`.
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//!
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//! The alignment of `CachePadded<T>` is the maximum of N bytes and the alignment of `T`.
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//!
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//! # Examples
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//!
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//! Alignment and padding:
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//!
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//! ```
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//! use cache_padded::CachePadded;
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//!
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//! let array = [CachePadded::new(1i8), CachePadded::new(2i8)];
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//! let addr1 = &*array[0] as *const i8 as usize;
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//! let addr2 = &*array[1] as *const i8 as usize;
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//!
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//! assert!(addr2 - addr1 >= 64);
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//! assert_eq!(addr1 % 64, 0);
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//! assert_eq!(addr2 % 64, 0);
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//! ```
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//!
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//! When building a concurrent queue with a head and a tail index, it is wise to place indices in
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//! different cache lines so that concurrent threads pushing and popping elements don't invalidate
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//! each other's cache lines:
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//!
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//! ```
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//! use cache_padded::CachePadded;
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//! use std::sync::atomic::AtomicUsize;
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//!
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//! struct Queue<T> {
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//! head: CachePadded<AtomicUsize>,
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//! tail: CachePadded<AtomicUsize>,
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//! buffer: *mut T,
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//! }
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//! ```
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#![no_std]
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#![forbid(unsafe_code)]
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#![warn(missing_docs, missing_debug_implementations, rust_2018_idioms)]
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#![deprecated(
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since = "1.3.0",
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note = "This crate is now deprecated in favor of [crossbeam-utils::CachePadded](https://docs.rs/crossbeam-utils/latest/crossbeam_utils/struct.CachePadded.html)."
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)]
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use core::fmt;
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use core::ops::{Deref, DerefMut};
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/// Pads and aligns data to the length of a cache line.
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// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
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// lines at a time, so we have to align to 128 bytes rather than 64.
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//
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// Sources:
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// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
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// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
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//
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// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
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//
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// Sources:
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// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
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//
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// powerpc64 has 128-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
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#[cfg_attr(
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any(
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target_arch = "x86_64",
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target_arch = "aarch64",
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target_arch = "powerpc64",
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),
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repr(align(128))
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)]
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// arm, mips, mips64, and riscv64 have 32-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
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#[cfg_attr(
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any(
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target_arch = "arm",
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target_arch = "mips",
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target_arch = "mips64",
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target_arch = "riscv64",
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),
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repr(align(32))
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)]
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// s390x has 256-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
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#[cfg_attr(target_arch = "s390x", repr(align(256)))]
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// x86 and wasm have 64-byte cache line size.
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//
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// Sources:
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// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
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// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
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//
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// All others are assumed to have 64-byte cache line size.
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#[cfg_attr(
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not(any(
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target_arch = "x86_64",
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target_arch = "aarch64",
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target_arch = "powerpc64",
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target_arch = "arm",
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target_arch = "mips",
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target_arch = "mips64",
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target_arch = "riscv64",
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target_arch = "s390x",
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)),
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repr(align(64))
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)]
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#[derive(Clone, Copy, Default, Hash, PartialEq, Eq)]
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pub struct CachePadded<T>(T);
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impl<T> CachePadded<T> {
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/// Pads and aligns a piece of data to the length of a cache line.
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///
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/// # Examples
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///
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/// ```
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/// use cache_padded::CachePadded;
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///
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/// let padded = CachePadded::new(1);
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/// ```
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pub const fn new(t: T) -> CachePadded<T> {
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CachePadded(t)
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}
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/// Returns the inner data.
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///
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/// # Examples
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///
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/// ```
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/// use cache_padded::CachePadded;
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///
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/// let padded = CachePadded::new(7);
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/// let data = padded.into_inner();
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/// assert_eq!(data, 7);
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/// ```
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pub fn into_inner(self) -> T {
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self.0
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}
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}
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impl<T> Deref for CachePadded<T> {
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type Target = T;
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fn deref(&self) -> &T {
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&self.0
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}
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}
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impl<T> DerefMut for CachePadded<T> {
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fn deref_mut(&mut self) -> &mut T {
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&mut self.0
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}
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}
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impl<T: fmt::Debug> fmt::Debug for CachePadded<T> {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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f.debug_tuple("CachePadded").field(&self.0).finish()
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}
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}
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impl<T> From<T> for CachePadded<T> {
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fn from(t: T) -> Self {
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CachePadded::new(t)
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}
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}
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