u-boot: improve compatibility with pci devices behind bridges
This commit is contained in:
Josua Mayer
parent
0042779f74
commit
0e699d9e48
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@ -0,0 +1,34 @@
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From 1742cdc4202d873af30ae3e4d3879092a7aead07 Mon Sep 17 00:00:00 2001
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From: Masami Hiramatsu <masami.hiramatsu@linaro.org>
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Date: Fri, 16 Apr 2021 14:53:46 -0700
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Subject: [PATCH 50/52] pci: Update the highest subordinate bus number for
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bridge setup
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Update the highest subordinate bus number after probing the devices
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under the bus for setting up the bridge correctly.
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The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
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removed this but it is required if a PCIe bridge is under the bus.
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Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
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Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
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---
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drivers/pci/pci-uclass.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
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index dfd54b339f..f463ef3550 100644
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--- a/drivers/pci/pci-uclass.c
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+++ b/drivers/pci/pci-uclass.c
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@@ -646,6 +646,9 @@ int dm_pci_hose_probe_bus(struct udevice *bus)
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return log_msg_ret("probe", ret);
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}
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+ if (!ea_pos)
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+ sub_bus = pci_get_bus_max();
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+
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dm_pciauto_postscan_setup_bridge(bus, sub_bus);
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return sub_bus;
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--
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2.35.3
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@ -0,0 +1,65 @@
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From 407e2364798f2f1714097a8efef08779f20d5c22 Mon Sep 17 00:00:00 2001
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From: Josua Mayer <josua@solid-run.com>
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Date: Wed, 3 Apr 2024 17:58:37 +0200
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Subject: [PATCH 51/52] pci: ls_pcie_g4: Wait 100ms for Link Up in
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ls_pcie_g4_probe
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PCI Link-up can be delayed especially with pci bridges or fpga starting
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up slowly.
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Add a 100ms delay during probe polling for link-up.
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Signed-off-by: Josua Mayer <josua@solid-run.com>
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---
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drivers/pci/pcie_layerscape_gen4.c | 21 ++++++++++++++++++++-
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1 file changed, 20 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
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index 255e73181d..9fe95268c4 100644
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--- a/drivers/pci/pcie_layerscape_gen4.c
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+++ b/drivers/pci/pcie_layerscape_gen4.c
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@@ -19,6 +19,9 @@
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#include "pcie_layerscape_gen4.h"
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+#define LINK_WAIT_RETRIES 100
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+#define LINK_WAIT_TIMEOUT 1000
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+
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DECLARE_GLOBAL_DATA_PTR;
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LIST_HEAD(ls_pcie_g4_list);
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@@ -50,6 +53,22 @@ static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
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return 1;
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}
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+static int ls_pcie_g4_wait_for_link(struct ls_pcie_g4 *pcie)
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+{
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+ int retries;
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+
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+ /* check if the link is up or not */
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+ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) {
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+ if (ls_pcie_g4_link_up(pcie)) {
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+ return 1;
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+ }
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+
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+ udelay(LINK_WAIT_TIMEOUT);
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+ }
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+
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+ return 0;
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+}
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+
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static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
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{
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ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
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@@ -550,7 +569,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
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val |= PPIO_EN;
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ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
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- if (!ls_pcie_g4_link_up(pcie)) {
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+ if (!ls_pcie_g4_wait_for_link(pcie)) {
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/* Let the user know there's no PCIe link */
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printf(": no link\n");
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return 0;
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--
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2.35.3
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@ -0,0 +1,59 @@
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From abada4616a827b556d2a4aa30533fa455c1cba81 Mon Sep 17 00:00:00 2001
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From: Josua Mayer <josua@solid-run.com>
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Date: Sun, 14 Apr 2024 16:45:42 +0200
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Subject: [PATCH 52/52] pci: ls_pcie: Wait 100ms for Link Up in ls_pcie_probe
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PCI Link-up can be delayed especially with pci bridges or fpga starting
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up slowly.
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Add a 100ms delay during probe polling for link-up.
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Signed-off-by: Josua Mayer <josua@solid-run.com>
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---
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drivers/pci/pcie_layerscape_rc.c | 21 ++++++++++++++++++++-
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1 file changed, 20 insertions(+), 1 deletion(-)
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diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
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index bd2c19f7f0..5f65667577 100644
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--- a/drivers/pci/pcie_layerscape_rc.c
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+++ b/drivers/pci/pcie_layerscape_rc.c
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@@ -19,8 +19,27 @@
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#endif
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#include "pcie_layerscape.h"
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+#define LINK_WAIT_RETRIES 100
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+#define LINK_WAIT_TIMEOUT 1000
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+
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DECLARE_GLOBAL_DATA_PTR;
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+static int ls_pcie_wait_for_link(struct ls_pcie *pcie)
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+{
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+ int retries;
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+
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+ /* check if the link is up or not */
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+ for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) {
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+ if (ls_pcie_link_up(pcie)) {
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+ return 1;
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+ }
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+
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+ udelay(LINK_WAIT_TIMEOUT);
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+ }
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+
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+ return 0;
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+}
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+
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static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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@@ -354,7 +373,7 @@ static int ls_pcie_probe(struct udevice *dev)
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"Root Complex");
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ls_pcie_setup_ctrl(pcie_rc);
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- if (!ls_pcie_link_up(pcie)) {
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+ if (!ls_pcie_wait_for_link(pcie)) {
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/* Let the user know there's no PCIe link */
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printf(": no link\n");
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return 0;
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--
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2.35.3
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